Instruction set architecture mode dependent sub-size access of register with associated status indication

A method comprising:

• storing data associated with a plurality of data types in a physical register file comprising a plurality of physical registers, said data types corresponding to at least two different sizes;
• storing an indication of a mode of at least two modes in a register;
• accessing said register to detect the mode of at least two modes that indicates whether instructions corresponding to a first instruction set architecture (ISA) are being processed or instructions corresponding to a second ISA different from the first ISA are being processed, wherein the first ISA does not support data operands with a size equal to a full size of a register of the plurality of registers and the second ISA does support data operands with a size equal to the full size of a register of the plurality of registers;
• in response to detecting a first mode of the at least two modes, determining a first instruction is associated with the first ISA, allowing access to a first portion of a given register of the plurality of physical registers identified by the first instruction and preventing access to a second portion of the given register;
• in response to detecting a second mode of the at least two modes, determining the first instruction is associated with the second ISA and allowing access to the full size of the given register;
• and
• in response to detecting the first mode and the given register is a destination register for the first instruction, storing a first indication corresponding to the given register that indicates the given register is being used to store a data operand associated with the first ISA.

A physical register file comprising:

• an array comprising a plurality of physical registers;
• an interface configured to receive array access requests;
• and
• access control logic;
• and
• wherein the access control logic is configured to:
• store an indication of a mode of at least two modes in a register;
• access said register to detect whether an instruction accessing the register file in a given clock cycle is associated with a first mode of the at least two modes rather than a second mode different from the first mode, wherein the first mode corresponds to a first instruction set architecture (ISA) that does not support data operands with a size equal to a full size of a register of the plurality of registers and the second ISA does support data operands with a size equal to the full size of a register of the plurality of registers;
• in response to detecting each instruction accessing the register file in the given clock cycle is associated with the first mode, prevent access to a first portion in each register of the plurality of physical registers;
• and
• in response to detecting each instruction accessing the register file in the given clock cycle is associated with the second mode, allow access a full register of each register of the plurality of physical registers;
• and
• in response to detecting each instruction accessing the register file in the given clock cycle is associated with the first mode, store a first indication corresponding to destination registers for each instruction that indicates the destination registers are being used to store data operands associated with the first ISA.

An apparatus comprising:

• control logic;
• and
• a physical register file including a plurality of physical registers;
• and
• wherein the control logic is configured to:
• store an indication of a mode of at least two modes in a register;
• access said register to detect whether an instruction accessing the register file in a given clock cycle is associated with a first mode of the at least two modes rather than a second mode different from the first mode, wherein the first mode corresponds to a first instruction set architecture (ISA) that does not support data operands with a size equal to a full size of a register of the plurality of registers and the second ISA does support data operands with a size equal to the full size of a register of the plurality of registers;
• in response to detecting the instruction is associated with the first mode:
• prevent a read access to a first portion of a register of the plurality of physical registers responsive to detecting an access is a read operation;
• and
• prevent an update of the first portion of the register of the plurality of physical registers responsive to detecting an access is a write operation;
• and
• in response to detecting the instruction is associated with the second mode, allow access of to a full size of the register of the plurality of physical registers;
• and
• in response to detecting the instruction is associated with the first mode, store a first indication corresponding to a destination register of the instruction that indicates the destination register is being used to store a data operand associated with the first ISA.