Vector hazard check instruction with reduced source operands
AssigneeApple Inc.
InventorsJeffry E. Gonion, Alexander C. Klaiber
Life of this patent
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Abstract
In an embodiment, a processor may implement a vector hazard check instruction to detect dependencies between vector memory operations based on the addresses of the vectors accessed by the vector memory operations. The addresses may be specified via a base address and a vector of indexes for each vector. In an embodiment, one of the base addresses may be an implied (or assumed) zero address, reducing the number of operands of the hazard check instruction.
Claims20
A processor comprising an execution core configured to execute an instruction having source operands that include a first scalar value and one or more vectors of indexes corresponding to a first vector memory operation and a second vector memory operation, wherein the execution core is configured to detect whether or not a dependency exists between the first vector memory operation and the second memory operation, wherein the detection of whether or not a dependency exists is based on the first scalar value and the one or more vectors of indexes, and wherein the execution core is configured to generate a dependency vector that indicates, for each first element of a first vector accessed by the first vector memory operation that depends on a second element of a second vector accessed by the second memory operation, which second element that the first element depends on.
A method comprising:
- a processor executing a first instruction to compute a difference between a first base address of a first vector and a second base address of a second vector;
- and
- the processor executing a second instruction having source operands that include the difference and one or more vectors of indexes corresponding to a first vector memory operation that accesses the first vector and a second vector memory operation that accesses the second vector, wherein executing the second instruction includes:
- detecting whether or not a dependency exists between the first vector memory operation and the second memory operation based on the difference and the one or more vectors of indexes;
- and
- generating a dependency vector that indicates, for each first element of the first vector that depends on a second element of the second vector, which second element that the first element depends on.
A processor comprising an execution core configured to execute an instruction having source operands that include one or more vectors of indexes corresponding to a first vector memory operation and a second vector memory operation and at least one vector attribute corresponding to a first vector accessed by the first vector memory operation, wherein the execution core is configured to detect whether or not a dependency exists between the first vector memory operation and the second memory operation, wherein the detection of whether or not a dependency exists is based on the vector attribute and the one or more vectors of indexes, and wherein the execution core is configured to generate a dependency vector that indicates, for each first element of a first vector accessed by the first vector memory operation that depends on a second element of a second vector accessed by the second memory operation, which second element that the first element depends on.
Dependencies are inferred from the claim text.