Shift register having multiple processing stages
AssigneeXilnix, Inc.
InventorRobert E. Payne
Life of this patent
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Abstract
In one embodiment, a shift register is provided. The LFSR includes a plurality of processing stages coupled in series, each configured to implement N taps of the LFSR. N single-tap circuits are coupled together in series and arranged to implement the last N taps of the LFSR. Each coefficient(s) of a feedback polynomial of the LFSR is implemented by one of the taps of the plurality of processing stages or the N single-tap circuits. A feedback generation circuit is configured to provide, for each of the plurality of processing stages, a respective feedback signal as a function of polynomial coefficients implemented by the processing stage and output from one or more of the N single tap circuits.
Claims20
A shift register, comprising:
- a plurality of M processing stages coupled in series, each processing stage configured to implement N taps of the shift register, wherein N>1, each coefficient of a feedback polynomial implemented by the shift register corresponding to respective one of the taps of the shift register;
- N single tap circuits coupled in series, a first of the N single tap circuits in the series coupled to an output of a last of the series of processing stages, and the N single tap circuits configured to implement the last N taps of the shift register;
- and
- a feedback control circuit configured to provide for one or more of the plurality of M processing stages, a respective 1-bit feedback signal as a function of polynomial coefficients implemented by the processing stage and data values input to one or more of the N single tap circuits.
A forward error correction (FEC) circuit, comprising:
- a linear feedback shift register (LFSR) configured to divide a sequence of symbols by a minimum polynomial to determine a set of remainders from the sequence of symbols;
- the LFSR including:
- a plurality of processing stages coupled in series, each processing stage configured to implement N taps of the LFSR, wherein N>1, each of the N taps corresponding to a respective coefficient of a feedback polynomial of the LFSR;
- N single tap circuits coupled in series, a first of the N single tap circuits in the series coupled to an output of a last of the series of processing stages, and the N single tap circuits configured to implement the last N taps of the LFSR;
- and
- a feedback control circuit configured to provide for one or more of the plurality of processing stages, a respective 1-bit feedback signal as a function of polynomial coefficients implemented by the processing stage and output from one or more of the N single tap circuits;
- and
- a syndrome calculation circuit configured to calculate a syndrome for each of the determined set of remainders.
A method of generating a circuit design comprising:
- inputting a code generation polynomial (G(x)) having L coefficients (0≦i<L);
- inputting a design parameter N;
- using a processor, generating, in response to the input code generation, an HDL circuit design specification of an LFSR for the code generation polynomial, the LFSR including:
- a plurality of processing stages coupled in series, each processing stage configured to implement N taps of the LFSR, the first L-N of the coefficients of the polynomial G(x) corresponding to respective ones of the taps implemented by the plurality of processing stages;
- N single tap circuits coupled in series, a first of the N single tap circuits in the series coupled to an output of a last of the series of processing stages, each of the last N of the coefficients of the polynomial G(x) corresponding to a respective one of the N single tap circuits;
- and
- a feedback control circuit configured to provide for one or more of the plurality of processing stages, a respective 1-bit feedback signal as a function of the coefficients implemented by the processing stage and N values input to the N single tap circuits;
- and
- storing the generated HDL circuit design specification in a computer readable medium.
Dependencies are inferred from the claim text.