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US 9,317,219 B2Granted
Semiconductor device and processor system including the same
AssigneeRenesas Electronics Corporation
InventorsDaisuke Kawakita, Toshikazu Hori
Life of this patent
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Abstract
Provided is a semiconductor device including: a plurality of processing circuits; an arbitration circuit that arbitrates a plurality of data transfer requests issued by the plurality of processing circuits; a mask control circuit that loads the plurality of data transfer requests arbitrated by the arbitration circuit, and sequentially outputs the plurality of data transfer requests after a lapse of a mask period; and a memory controller that accesses a memory based on the plurality of data transfer requests sequentially output from the mask control circuit, and switches a mode of the memory to a power saving mode when no data transfer request is output from the mask control circuit for a predetermined period.
Claims13
A semiconductor device comprising:
- a plurality of processing circuits;
- an arbitration circuit that arbitrates a plurality of data transfer requests issued by the plurality of processing circuits;
- a mask control circuit that loads the plurality of data transfer requests arbitrated by the arbitration circuit, and sequentially outputs the plurality of data transfer requests after a lapse of a mask period;
- and
- a memory controller that accesses a memory based on the plurality of data transfer requests sequentially output from the mask control circuit, and switches a mode of the memory to a power saving mode when no data transfer request is output from the mask control circuit for a predetermined period,
- wherein the mask control circuit comprises
- a mask signal generation circuit that generates a mask signal, the mask signal being periodically switched between an active state and an inactive state;
- and
- a transfer request output circuit coupled to the arbitration circuit which receives the mask signal that sequentially outputs the plurality of loaded data transfer requests to the memory controller when the mask signal is in the inactive state.
6 more elements
A semiconductor device comprising:
- a plurality of processing circuits;
- an arbitration circuit that arbitrates a plurality of data transfer requests issued by the plurality of processing circuits;
- a mask control circuit that loads the plurality of data transfer requests arbitrated by the arbitration circuit, and sequentially outputs the plurality of data transfer requests after a lapse of a mask period;
- and
- a memory controller that accesses a memory based on the plurality of data transfer requests sequentially output from the mask control circuit, and switches a mode of the memory to a power saving mode when no data transfer request is output from the mask control circuit for a predetermined period,
- wherein the mask control circuit comprises
- a first monitor that monitors a total amount of data on data transfer requests issued by the plurality of processing circuits during a monitoring period;
- a second monitor that monitors a total amount of data that can be accepted by the memory;
- a mask signal generation unit that generates a mask signal, the mask signal being periodically switched between an active state and an inactive state;
- and
- a transfer request output unit that sequentially outputs the plurality of loaded data transfer requests when the mask signal is in the inactive state, and
- wherein the mask signal generation unit sets a length of an active period of the mask signal as the mask period, based on monitoring results of the first and second monitors.
9 more elements
A semiconductor device comprises:
- a plurality of processing circuits;
- an arbitration circuit that arbitrates a plurality of data transfer requests issued by the plurality of processing circuits;
- a mask control circuit that loads the plurality of data transfer requests arbitrated by the arbitration circuit, and sequentially outputs the plurality of data transfer requests after a lapse of a mask period;
- and
- a memory controller that accesses a memory based on the plurality of data transfer requests sequentially output from the mask control circuit, and switches a mode of the memory to a power saving mode when no data transfer request is output from the mask control circuit for a predetermined period,
- wherein each of the processing circuits issues a data transfer request, and issues priority information indicating a priority of the data transfer request,
- wherein the mask control circuit outputs the loaded data transfer request after a lapse of a mask period of a length set according to the priority of the data transfer request,
- wherein the mask control circuit comprises
- a mask signal generation unit that generates a mask signal, the mask signal being periodically switched between an active state and an inactive state;
- a transfer request output unit that outputs the loaded data transfer request when the mask signal is in the inactive state;
- and
- a priority information storage unit that stores the priority information, and
- wherein the mask signal generation unit sets a length of an active period of the mask signal as the mask period, based on the priority information stored in the priority information storage unit.
10 more elements
Dependencies are inferred from the claim text.