Accelerated cache rinse when preparing a power state transition

An apparatus, comprising:

• a compute unit comprising a cache, wherein the compute unit is configured to indicate it is attempting to enter a low power state and flush at least one modified line of the cache subsequent the indication;
• a power management unit configured to permit the compute unit to enter the low power state;
• and
• a cache rinser configured to detect at least one line of the cache that differs from a corresponding line in a memory and write differing data from the at least one differing line to the memory, wherein the cache rinser is configured to detect and write at a first frequency prior to the indication by the compute unit and at a second frequency subsequent the indication, and the second frequency is higher than the first frequency.

A non-transitory computer-readable medium storing instructions executable by at least one processor to fabricate an apparatus, the apparatus comprising:

• a compute unit comprising a cache, wherein the compute unit is configured to indicate it is attempting to enter a low power state and flush at least one modified line of the cache subsequent the indication;
• a power management unit configured to permit the compute unit to enter the low power state;
• and
• a cache rinser configured to detect at least one line of the cache differing from a corresponding line in a memory and write differing data from the at least one differing line to the memory, wherein the cache rinser is configured to detect and write at a first frequency prior to the indication by the compute unit and at a second frequency subsequent the indication, wherein the second frequency is higher than the first frequency.