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US 9,317,089 B2Granted
Mesh performance improvement using dual voltage data transfer
AssigneeIntel Corporation
InventorsNazar S. Haider, Donald C. Soltis, Jr.
Life of this patent
Estimating the term…
Abstract
Methods and apparatus relating to techniques for mesh performance improvement using dual voltage data transfer are described. In one embodiment, a first plurality of signal paths are operated at a higher voltage level than a second plurality of signal paths. The first plurality of signal paths comprises Resistor-Capacitor (RC) dominated signal paths that move signals between any two system tiles. Other embodiments are also disclosed.
Claims23
An apparatus comprising:
- a first tile including a first processor core and a first cache;
- a second tile including a second processor core and a second cache;
- logic to cause a first plurality of signal paths between the first tile and the second tile to operate at a higher voltage level than a second plurality of signal paths associated with the first tile and the second tile, wherein the first plurality of signal paths are to comprise Resistor-Capacitor (RC) dominated signal paths that are to move signals between the first and the second tiles, wherein the logic is to cause only a portion of the first plurality of signal paths that includes combinatorial logic to operate at the higher voltage level.
A method comprising:
- causing a first plurality of signal paths to operate at a higher voltage level than a second plurality of signal paths, wherein the first plurality of signal paths comprise Resistor-Capacitor (RC) dominated signal paths that move signals between any two system tiles;
- and
- causing only a portion of the first plurality of signal paths that includes combinatorial logic to operate at the higher voltage level.
A system comprising:
- a processor having one or more processor cores;
- a power supply coupled to the processor;
- and
- logic, coupled to the power supply, to cause a first plurality of signal paths to operate at a higher voltage level than a second plurality of signal paths,
- wherein the first plurality of signal paths are to comprise Resistor-Capacitor (RC) dominated signal paths that move signals between any two system tiles, wherein the logic is to cause only a portion of the first plurality of signal paths that includes combinatorial logic to operate at the higher voltage level.
2 more elements
An apparatus comprising:
- a plurality of tiles coupled to one or more data paths to move data between the plurality of tiles, each of the plurality of tiles to include a processor core and a cache, wherein the one or more data paths is to operate at a higher voltage than an internal path of a particular tile of the plurality of tiles in a first mode, and wherein the internal path of the particular tile is to operate at a higher voltage than the one or more data paths in a second mode;
- and
- control logic coupled to the particular tile to drive signals on the one or more data paths through a level shifter in the first mode and to bypass the level shifter and drive signals on the one or more data paths in the second mode, wherein the control logic is to cause only a portion of the one or more data paths that includes combinatorial logic to operate at the higher voltage level.
Dependencies are inferred from the claim text.