Memory column drowsy control

A method comprising:

• storing a stored datum in a memory cell comprising a power supply node for receiving power to operate the memory cell;
• and
• providing power to the power supply node at a first voltage level to cause the memory cell to be capable of read and write operations in response to either a power saving control signal being inactive or a power control memory cell being in a first state when the power saving control signal is active and at a second voltage level to cause the memory cell to enter a stored datum retention mode wherein the memory cell retains the stored datum while consuming reduced power in response to the power saving control signal being active and the power control memory cell being in a second state when the power saving control signal is active, wherein the power control memory cell stores a power control datum to select a reduced voltage level for a normal column of a plurality of memory cells comprising the memory cell, wherein the normal column consists of normal memory cells capable of memory retention at the reduced voltage level, wherein a second power control memory cell stores a second power control datum to select a full voltage level for a weak column of the plurality of memory cells, wherein the weak column includes at least one weak memory cell incapable of memory retention at the reduced voltage level.