Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same
AssigneeLG Display Co., Ltd.
InventorMunGi Park
Life of this patent
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Abstract
The present disclosure relates to an array substrate for a fringe field switching mode liquid crystal display device, and a fabricating method thereof, the array substrate including a gate line on an insulating substrate, an active layer on a gate electrode, a data line having a source electrode on one side of the active layer, the data line defining a pixel region, a large pixel electrode on another side of the active layer, a planarization layer on the data line and the source electrode, a passivation layer formed on the insulating substrate, and a common electrode on the passivation layer, and overlapping the pixel electrode and the data line.
Claims9
An array substrate for a fringe field switching mode liquid crystal display device, the array substrate comprising:
- a gate line formed on one surface of an insulating substrate in one direction;
- an active layer formed on a gate electrode extending from the gate line;
- a data line having a source electrode formed on one side of the active layer, the data line defining a pixel region by intersecting with the gate line;
- a large pixel electrode formed on another side of the active layer, spaced from the source electrode, and on the pixel region of the insulating substrate;
- a planarization layer formed only on the data line and the source electrode;
- a passivation layer formed on an entire surface of the insulating substrate having the planarization layer;
- and
- a common electrode formed on the passivation layer, and overlapping the pixel electrode and the data line.
A method for fabricating an array substrate for a fringe field switching mode liquid crystal display device, the method comprising:
- forming a gate line, a gate pad and a data pad on one surface of an insulating substrate in one direction;
- forming an active layer on a gate electrode extending from the gate line;
- forming a data line defining a pixel region by intersecting with the gate line, the data line having a source electrode disposed on one side of the active layer;
- forming a large pixel electrode on another side of the active layer, spaced from the source electrode, and on the pixel region of the insulating substrate;
- forming a planarization layer only on the data line and the source electrode;
- forming a passivation layer on an entire surface of the insulating substrate having the planarization layer;
- forming a gate pad contact hole and a data pad contact hole on the passivation layer, the gate pad contact hole and the data pad contact hole exposing the gate pad and the data pad, respectively;
- and
- forming a common electrode on the passivation layer, the common electrode overlapping the pixel electrode and the data line.
Dependencies are inferred from the claim text.