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US 9,316,692 B2Granted
Tap clock and enable control of scan register, flip-flop, comparator
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.
Claims4
A device comprising:
- A. a scan data input lead;
- B. a test clock lead;
- C. a test mode select lead;
- D. a test access port having a clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, a scan clock output, and a scan enable output;
- E. a scan register having a scan input coupled to the scan data input lead, a scan clock input coupled to the scan clock output, a control input coupled to the scan enable output, and a scan output;
- F. an inverter having an input connected to the test clock lead and an inverted test clock output;
- G. a flip flop having a data input coupled to the scan data input lead, a clock input coupled to the inverted test clock output, and a data output;
- and
- H. a compare circuitry having a first data input coupled to the scan output of the scan register and a second data input coupled to the data output of the flip flop.
6 more elements
Dependencies are inferred from the claim text.