Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

An apparatus to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one or more capture clocks and one or more scan cells;

• said apparatus comprising:
• (a) an input pattern generator for generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift operation;
• (b) a capture clock pulse generator for applying an ordered sequence of capture clock pulses to all said scan cells within said N clock domains during a capture operation, the ordered sequence of capture clock pulses comprising at least two capture clock pulses from two or more selected capture clocks, for controlling two or more clock domains, in a sequential order, wherein each said selected capture clock must contain at least one said capture clock pulse, and when detecting or locating selected delay faults within a clock domain, said selected capture clock controlling the clock domain contains at least two consecutive said capture clock pulses to launch the transition and capture the output response;
• and (c) an output response analyzer for analyzing output responses of all said scan cells to detect or locate said faults therein.