Substrate having electronic component embedded therein and method of manufacturing the same

A substrate having an electronic component embedded therein, comprising:

• a first insulating layer including a cavity and having first and second circuit patterns provided on upper and lower surfaces thereof, respectively;
• the electronic component at least partially inserted into the cavity and including an external electrode;
• a plurality of build-up insulating layers stacked on top or beneath the first insulating layer;
• upper and lower circuit patterns formed on the build-up insulating layers, respectively;
• and
• a plurality of vias interconnecting the external electrode, the upper circuit pattern, the first circuit pattern, the second circuit pattern, and the lower circuit pattern to one another to form an electrical loop,
• wherein at least one of the upper circuit patterns forming the electrical loop is simultaneously connected with at least two of the plurality of vias, and
• wherein at least one of the lower circuit patterns forming the electrical loop is simultaneously connected with at least two of the plurality of vias.

A method of manufacturing a substrate having an electronic component embedded therein, the method comprising:

• providing a first insulating layer including a cavity;
• inserting at least a portion of the electronic component including an external electrode into the cavity, forming a first circuit pattern on an upper surface of the first insulating layer, forming a second circuit pattern on a lower surface of the first insulating layer, and forming a third via directly connecting the first circuit pattern and the second circuit pattern to each other while penetrating through the first insulating layer;
• forming a plurality of build-up insulating layers on and beneath the first insulating layer, respectively;
• forming a plurality of via holes penetrating the plurality of build-up insulating layers;
• and
• filling conductive materials in the plurality of via holes to form a plurality of vias and forming an upper circuit pattern and a lower circuit pattern on the build-up insulating layers, respectively,
• wherein the external electrode, the upper circuit pattern, the first circuit pattern, the second circuit pattern, and the lower circuit pattern are interconnected to one another by the plurality of vias to form an electrical loop
• wherein at least one of the upper circuit patterns forming the electrical loop is simultaneously connected with at least two of the plurality of vias, and at least one of the lower circuit patterns forming the electrical loop is simultaneously connected with at least two of the plurality of vias.

A substrate having an electronic component embedded therein, comprising:

• a first insulating layer including a cavity;
• a second insulating layer stacked on an upper surface of the first insulating layer;
• a third insulating layer stacked on a lower surface of the first insulating layer;
• the electronic component at least partially inserted into the cavity and including an external electrode;
• a circuit pattern on an upper surface of the second insulating layer;
• a first via penetrating through a portion of the second insulating layer above the electronic component and connecting the external electrode with the circuit pattern;
• a second via connected to the circuit pattern and penetrating through the second insulating layer;
• a third via penetrating through a portion of the first insulating layer outside the cavity, connected to the second via, and positioned under a portion of the second via;
• a fourth via penetrating through the third insulating layer, connected to the third via, and positioned under a portion of the third via;
• and
• a fifth via directly connecting the external electrode and the fourth circuit pattern to each other while penetrating through the third insulating layer,
• wherein an electrical loop is formed by connections from the external electrode to the third circuit pattern through the first via, from the third circuit pattern to the first circuit pattern through the second via, from the first circuit pattern to the second circuit pattern through the third via, from the second circuit pattern to the fourth circuit pattern through the fourth via, and from the fourth circuit pattern to the external electrode through the fifth via.