DC coefficient signaling at small quantization step sizes
AssigneeMicrosoft Technology Licensing, LLC
InventorsChih-Lung Lin, Shankar Regunathan, Sridhar Srinivasan
Life of this patent
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Abstract
Described tools and techniques relate to signaling for DC coefficients at small quantization step sizes. The techniques and tools can be used in combination or independently. For example, a tool such as a video encoder or decoder processes a VLC that indicates a DC differential for a DC coefficient, a FLC that indicates a value refinement for the DC differential, and a third code that indicates the sign for the DC differential. Even with the small quantization step sizes, the tool uses a VLC table with DC differentials for DC coefficients above the small quantization step sizes. The FLCs for DC differentials have lengths that vary depending on quantization step size.
Claims29
A method of coding/decoding video, the method comprising, with a computing device that implements a video encoder and/or video decoder:
- determining a quantization step size, wherein one or more syntax elements in a bit stream indicate the quantization step size;
- processing a variable length code (VLC) for a DC differential for a DC coefficient using a VLC table that includes different VLC values associated with different values for the DC differential, wherein the VLC table further includes an escape code that indicates presence of a fixed length code (FLC) for the DC differential for the DC coefficient;
- and
- when the VLC is the escape code:
- using the quantization step size to determine a length of the FLC for the DC differential for the DC coefficient, wherein the length of the FLC varies depending on the quantization step size;
- and
- processing the FLC for the DC differential for the DC coefficient.
A computer-implemented method of decoding video using a computing device that implements a video decoder, the method comprising, with the computing device that implements the video decoder:
- determining a quantization step size for a block of a video picture based on one or more syntax elements in a bit stream;
- receiving a variable length code (VLC) in the bit stream, wherein the VLC at least in part indicates a DC differential for a DC coefficient of the block of the video picture;
- determining that the VLC indicates an escape code in a VLC table, the escape code indicating presence in the bit stream of a fixed length code (FLC) for the DC differential, the VLC table also including different VLC values associated with different values for DC differentials;
- using the quantization step size to determine a length of the FLC for the DC differential in the bit stream, wherein the length of the FLC varies depending on the quantization step size;
- receiving the FLC in the bit stream;
- and
- decoding the FLC to determine a value for the DC differential;
- and
- reconstructing the DC coefficient using the value for the DC differential, wherein the DC differential represents a difference between the DC coefficient and a DC predictor.
A computing device comprising a processor and memory, wherein the computing device implements a video decoder configured to perform operations comprising:
- determining a quantization step size for a block of a video picture based on one or more syntax elements in a bit stream;
- receiving a variable length code (VLC) in the bit stream, wherein the VLC at least in part indicates a DC differential for a DC coefficient of the block of the video picture;
- determining that the VLC indicates an escape code in a VLC table, the escape code indicating presence in the bit stream of a fixed length code (FLC) for the DC differential, the VLC table also including different VLC values associated with different values for DC differentials;
- using the quantization step size to determine a length of the FLC for the DC differential in the bit stream, wherein the length of the FLC varies depending on the quantization step size;
- receiving the FLC in the bit stream;
- decoding the FLC to determine a value for the DC differential;
- and
- reconstructing the DC coefficient using the value for the DC differential, wherein the DC differential represents a difference between the DC coefficient and a DC predictor.
One or more computer-readable memory devices storing computer-executable instructions for causing a computer system programmed thereby to perform decoding operations comprising:
- determining a quantization step size for a block of a video picture based on one or more syntax elements in a bit stream;
- receiving a variable length code (VLC) in the bit stream, wherein the VLC at least in part indicates a DC differential for a DC coefficient of the block of the video picture;
- determining that the VLC indicates an escape code in a VLC table, the escape code indicating presence in the bit stream of a fixed length code (FLC) for the DC differential, the VLC table also including different VLC values associated with different values for DC differentials;
- using the quantization step size to determine a length of the FLC for the DC differential in the bit stream, wherein the length of the FLC varies depending on the quantization step size;
- receiving the FLC in the bit stream;
- decoding the FLC to determine a value for the DC differential;
- and
- reconstructing the DC coefficient using the value for the DC differential, wherein the DC differential represents a difference between the DC coefficient and a DC predictor.
Dependencies are inferred from the claim text.