Compact and fast N-factorial single data rate clock and data recovery circuits

A method operational on a receiver circuit, comprising:

• receiving a spread signal distributed over a plurality of line interfaces, the spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols, the spread signal defined by a plurality of state transition signals including a first signal over a first line interface and a second signal over a second line interface;
• obtaining a clock signal based on a comparison between a first instance of the first signal and a delayed second instance of the first signal, and a comparison between a first instance of the second signal and a delayed second instance of the second signal;
• and
• sampling the delayed second instance of the first signal based on the clock signal to provide a symbol output.

A receiver circuit, comprising:

• means for receiving a spread signal distributed over a plurality of line interfaces, the spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols, the spread signal defined by a plurality of state transition signals including a first signal over a first line interface and a second signal over a second line interface;
• means for obtaining a clock signal based on a comparison between a first instance of the first signal and a delayed second instance of the first signal, and a comparison between a first instance of the second signal and a delayed second instance of the second signal;
• and
• means for sampling the delayed second instance of the first signal based on the clock signal to provide a symbol output.