Circuits for and methods of filtering inter-symbol interference for SerDes applications

A circuit for filtering inter-symbol interference in an integrated circuit, the circuit comprising:

• a decision feedback equalizer coupled to receive digital samples of an input signal, wherein the decision feedback equalizer generates first decision outputs at an output of a first decision block based upon the digital samples;
• a multiplier coupled to the output of the first decision block of the decision feedback equalizer and a scalar value;
• a feed forward equalizer coupled to receive the first decision outputs and to generate detected inter-symbol interference associated with the first decision outputs;
• a pre-filter coupled to receive delayed digital samples of the input signal;
• a first subtractor circuit coupled to an output of the pre-filter and an output of the feed forward equalizer;
• and
• a second decision block coupled to an output of the subtractor circuit, the second decision block generating second decision outputs.

A method of filtering inter-symbol interference in an integrated circuit, the method comprising:

• receiving digital samples of an input signal at a first stage;
• generating first decision outputs of the first stage based upon the digital samples;
• generating filtered decisions of the first decision outputs;
• receiving the digital samples of the input signal at a second stage;
• coupling the digital samples to a delay element to generate delayed digital samples;
• coupling the delayed digital samples to a pre-filter of the second stage, wherein the delay element aligns an output of the pre-filter that is filtered before inter-symbol interference cancellation with the filtered decisions of the first decision outputs;
• and
• generating second decision outputs based upon the delayed digital samples of the input signal and detected inter-symbol interference associated with the filtered decisions of the first decision outputs.