Multi-channel timing recovery device

A multi-channel timing recovery device capable of generating a common clock for dealing with a plurality of data channel signals, comprising:

• a first channel timing recovery circuit operable to generate the common clock, including:
• a first detecting circuit capable of detecting phase and/or frequency and operable to detect a first channel signal according to a first clock to thereby generate a first detection signal;
• an oscillation control circuit operable to generate an oscillation control signal according to the first detection signal, including one of the follows:
• a combination of a timing-to-digital converter and a first digital filter, a combination of a first charge pump and a first analog filter, and a digital filter;
• an oscillator operable to generate the common clock according to the oscillation control signal;
• and
• a feedback circuit operable to provide the first clock according to the common clock;
• and
• a second channel timing recovery circuit operable to generate a second clock according to the common clock, including:
• a second phase detecting circuit operable to detect a second channel signal according to the second clock and thereby generate a second phase detection signal;
• a second phase control circuit operable to generate a second phase control signal according to the second phase detection signal;
• and
• a second clock output circuit operable to generate the second clock according to the common clock and determine the phase of the second clock according to the second phase control signal;
• and
• a selecting circuit operable to receive one of the first detection signal and the derived signal thereof and receive one of the second phase detection signal and the derived signal thereof, and output the first detection signal or the derived signal thereof to one of the oscillation control circuit and the oscillator according to a selection control signal.