Receiver circuit, communication system, electronic device, and method for controlling receiver circuit

A method for controlling a receiver circuit for capturing an input signal at a plurality of capture timings determined based on a capture clock signal, comprising:

• a delay control step of delaying the input signal changing to a first state or a second state by a set delay time, and outputting the delayed input signal;
• a latch step of capturing the input signal delayed by the delay control step at each capture timing;
• a data test step of testing a latch signal captured by the latch step;
• and
• a delay value adjustment step of adjusting the delay time based on a test result of the data test step,
• wherein
• in the data test step, the latch signal captured at each capture timing is compared with an expected value, and includes a first cross-point detection step of, when it is determined based on the test result value that a period of time during which the first or second state continues is longer than a cycle of the capture timing, detecting a deviation of a cross point of the input signal input as differential signals.

A receiver circuit for capturing an data signal at a plurality of capture timings determined based on a capture clock signal, comprising:

• a delay circuit configured to delay the data signal changing to a first state or a second state by a set delay time, and output the delayed data signal;
• a latch circuit configured to capture the data signal delayed by the delay circuit at each capture timing;
• a data test circuit configured to test a latch signal captured by the latch circuit;
• and
• a data test result register configured so that a test result value corresponding to a test result of the data test circuit is set therein,
• wherein
• the data test circuit compares the latch signal captured by the latch circuit at each capture timing with an expected value, and outputs the result of the comparison.

A method for controlling a receiver circuit for capturing a data signal at a plurality of capture timings

• determined based on a capture clock signal, comprising:
• a delay control step of delaying the data signal changing to a first state or a second state by a set delay time, and outputting the delayed data signal;
• a latch step of capturing the data signal delayed by the delay control step at each capture timing;
• a data test step of testing a latch signal captured by the latch step;
• and
• a delay value adjustment step of adjusting the delay time based on a test result of the data test step,
• wherein
• in the data test step, the latch signal captured at each capture timing is compared with an expected value.