Loading patent…
AssigneeKabushiki Kaisha Toshiba
InventorsKenji Sakaue, Yoshihisa Kondo, Tarou Iwashiro
Estimating the term…
According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.
A memory system comprising:
An error correction method of a memory system comprising a memory cell array which includes a first storage area configured to store therein 1-bit data in one memory cell, and a second storage area configured to store therein data of a plurality of bits in one memory cell, to which the data is written in units of pages, and from which the data is read in units of pages, the second storage area including a plurality of blocks each of which is constituted of a plurality of pages, each of the plurality of blocks including an area configured to store therein data of the first storage area, and a redundant area including a page,
Dependencies are inferred from the claim text.