Double QC-LDPC code

A processor corresponding to a double quasi-cyclic low density parity check (DQC-LDPC) code, wherein the processor comprises:

• an input end configured to receive an input signal:
• an output end configured to output an output signal:
• and
• a processing module configured to process the input signal to generate the output signal corresponding to a parity-check matrix of the DQC-LDPC code,
• wherein the parity-check matrix comprises a double quasi-cyclic (DQC) matrix, the double quasi-cyclic matrix comprises a plurality of sub-matrices, the sub-matrices are arranged in an array, each sub-matrix comprises a plurality of entries, each sub-matrix is a circulant matrix having the entries circular shifted pow-by-row, and the double quasi-cyclic matrix is a circulant matrix having the submatrices ircular shifted row-by-row:
• wherein the parity-check matrix has n×q columns of the entries and m×q rows of the entries, the double quasi-cyclic matrix has m columns of sub-matrices and m rows of sub-matrices, each of the sub-matrices has q columns of the entries and q rows of the entries, the double quasi-cyclic matrix is presented as DQC in an equation below, and the entries in the double quasi-cyclic matrix are conformed to the equation:
• DQC[((i±x)mod m)×q+((j±y)mod q)][x×q±y]=DQC[i×q±j][0],
• where i, j, x, y are integers, 0≦i<m, 0≦j<q, 0≦x<m, and 0≦y<q.