Analog-to-digital converter and image sensor

An analog-to-digital converter comprising:

• a sampler to hold a sampled signal obtained by sampling an input signal for each specific time;
• an input signal predictor to generate a prediction signal before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal;
• a comparator to compare the signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal level of the sampled signal;
• a first counter to perform a count operation in synchronism with a first clock signal when the comparator starts a comparison operation;
• and
• a second counter to perform a count operation in synchronism with a second clock signal having a higher frequency than the first clock signal after the generation of the prediction signal and to increase or decrease a count value in accordance with the comparison signal,
• wherein the input signal predictor comprises a bias signal generator to generate a bias signal obtained by converting the signal level of the ramp signal or the sampled signal, and
• the comparator comprises:
• a first comparator to compare signal levels of the sampled signal or ramp signal and the bias signal to output a comparison signal showing whether the signal level of the bias signal is larger than the signal level of the sampled signal or the ramp signal;
• and
• a second comparator to compare signal levels of the sampled signal and the ramp signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal level of the sampled signal,
• wherein the second counter starts a count operation when the first comparator detects that the signal level of the sampled signal or ramp signal cross with the signal level of the bias signal and increases or decreases a count value in accordance with the comparison signal of the second comparator.

An analog-to-digital converter comprising:

• a sampler to hold a sampled signal obtained by sampling an input signal for each specific time;
• an input signal predictor to generate a prediction signal before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal;
• a comparator to compare the signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal level of the sampled signal;
• a first counter to perform a count operation in synchronism with a first clock signal when the comparator starts a comparison operation;
• and
• a second counter to perform a count operation in synchronism with a second clock signal having a higher frequency than the first clock signal after the generation of the prediction signal and to increase or decrease a count value in accordance with the comparison signal of the comparator,
• wherein the input signal predictor comprises a bias signal generator to generate a bias signal obtained by converting the signal level of the ramp signal or the sampled signal, and
• the comparator comprises:
• a first comparator to compare signal levels of the sampled signal or ramp signal and the bias signal to output a signal showing whether the signal level of the bias signal is larger than the signal level of the sampled signal or the ramp signal;
• a second comparator to compare signal levels of the sampled signal and the ramp signal to output a signal showing whether the signal level of the ramp signal is larger than the signal level of the sampled signal;
• and
• a power switch to be switched to supply a power to the second comparator or not based on the comparison signal of the first comparator,
• wherein the second counter starts a count operation when the first comparator detects that the signal level of the sampled signal or ramp signal crosses with the signal level of the bias signal and increases or decreases a count value in accordance with the comparison signal of the second comparator.