Clock phase adjusting circuit and semiconductor device including the same
AssigneeSK hynix Inc.
InventorDae-Suk Kim
Life of this patent
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Abstract
A semiconductor device includes a buffer suitable for receiving an input signal, a clock buffer suitable for receiving a clock, a delay locked loop (DLL) suitable for delaying the clock to generate a delay locked clock, a code generation unit suitable for generating a digital code corresponding to 1/N of the clock cycle where N is an integer equal to or more than two, a delay unit suitable for delaying the clock corrected by the DLL by a value corresponding to the digital code to output a delayed clock, and a strobing unit suitable for strobing the input signal using the delayed clock.
Claims12
A semiconductor device comprising:
- a data buffer suitable for receiving an input signal from an external;
- a clock buffer suitable for receiving a clock;
- a first path suitable for transmitting the input signal from the data buffer;
- a second path suitable for transmitting the clock from the clock buffer;
- a delay locked loop (DLL) suitable for delaying the clock from the second path to generate a delay locked clock;
- a code generation unit suitable for generating a digital code corresponding to 1/N of the clock cycle where N is an integer equal to or more than two;
- a delay unit suitable for delaying the delay locked clock from the DLL by a value corresponding to the digital code to output a delayed clock;
- a third path suitable for transmitting the delayed clock from the delay unit;
- and
- a strobing unit suitable for strobing the input signal from the first path using the delayed clock from the third path,
- wherein the DLL delays the clock by [(M*tCK)−(B+C−A)], where M is an integer equal to or more than one, tCK is one cycle of the clock, B is a delay value of the second path, C is a delay value of the third path, and A is a delay value of the first path.
A semiconductor device comprising:
- a data buffer suitable for receiving an input signal from an external;
- a clock buffer suitable for receiving a clock;
- a first path suitable for transmitting the input signal from the data buffer;
- a second path suitable for transmitting the clock from the clock buffer;
- a code generation unit suitable for generating a digital code corresponding to 1/N of the clock cycle where N is an integer equal to or more than two;
- a delay unit suitable for delaying the clock from the second path by a value corresponding to the digital code to output a delayed clock;
- a DLL suitable for delaying the delayed clock and to generate a delay locked clock;
- a third path suitable for transmitting the delay locked clock from the DLL;
- and
- a strobing unit suitable for strobing the input signal from the first path using the delayed locked clock from the third path,
- wherein the DLL delays the delayed clock by [(M*tCK)−(B+C−A)], where M is an integer equal to or more than one, tCK is one cycle of the clock, B is a delay value of the second path, C is a delay value of the third path, and A is a delay value of the first path.
Dependencies are inferred from the claim text.