Phase lock loop (PLL/FLL) clock signal generation with frequency scaling to power supply voltage

#The present invention is generally related to techniques to modify the output clock frequency of a clock signal generation circuit to address the problems caused by voltage droop and overshoot of a power supply.

#FIG. 1 illustrates a conventional Phase Locked Loop (PLL) clock signal generation circuit 100 of the prior art. A PLL 105 used to generate a clock signal 106 from an input clock reference signal 107. A similar clock signal generation circuit 100 without PFD (110) is also sometimes described as a Frequency Locked Loop (FLL).

#A PLL is typically used in digital system to provide a clock signal having a frequency programmed at the operating frequency of the digital system, as shown in FIG. 1. The PLL circuit includes a Phase Frequency Detector (PFD) 110, charge pump 115, loop filter 120, voltage controlled oscillator 125, and a divider 130.

#FIG. 1 illustrates a prior art PLL clock generation circuit.

#FIG. 2 illustrates a prior art Nehalem approach to partially adapt a PLL clock generation circuit to power supply voltage transients.

#FIG. 3 is a high level block diagram a PLL/FLL circuit of the present invention in accordance with an embodiment of the present invention.

#The present invention is generally directed to systems, methods, and circuits for an improved Dynamic Voltage Frequency Scaling (DVFS) PLL/FLL to adapt a clock frequency to power supply transients. The clock frequency supplied to a digital circuit is dynamically scaled to track changes in VDD power supply noise as a digital system operates. The clock frequency is dynamically scaled to track at least the lower frequency (slow path) VDD transients. One aspect is that adapting the clock frequency helps to avoid setup/hold time in a digital system with significant noise present on its VDD supply and offers potential performance advantages in terms of speed and power.

#Block Diagrams

#FIG. 3 is a block diagram of a Dynamic Voltage Frequency Scaling (DVFS) PLL/FLL 300 in accordance with an embodiment of the present invention. The DVFS PLL/FLL 300 is a noise aware PLL circuit. The PLL circuit supplies a clock signal to a digital system 390 having a power supply voltage of VDD. As the digital system 390 operates the current (i) of the digital system switches and there will be di/dt noise associated with the impedance of the packaged digital system. The impedance includes capacitive and inductive components, which in turn generate 1st and 2nd order droops. In modern graphics systems the nominal VDD can be close to 1 V and the droop can exceed 200 mV if a fixed clock frequency is used.