US 9,312,864 B2 · AFLL with increased timing margin

Abstract

In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.

Claims18

Dependent claims

An integrated circuit, comprising a first sub-frequency-locked loop in an asymmetric frequency-locked loop (AFLL) that provides a clock signal, wherein the first sub-frequency-locked loop includes:

a first digitally controlled oscillator (DCO) configured to output a first signal having a first fundamental frequency;
a second DCO configured to output a second signal having a second fundamental frequency;
a voltage regulator that provides a power-supply voltage to the second DCO;
and
control logic, electrically coupled to the first DCO and the second DCO, configured to select one of the first DCO and the second DCO based on an instantaneous value of the power-supply voltage and an average power-supply voltage, wherein the AFLL is configured to modify a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage, wherein the first DCO is associated with a time-critical path having a gate-dominated delay characteristic and the second DCO is associated with a time-critical path having a wire-dominated delay characteristic.

2 more elements

An electronic device, comprising:

a processor;
a memory storing a program module that is configured to be executed by the processor;
and
an integrated circuit, wherein the integrated circuit includes a first sub-frequency-locked loop in an asymmetric frequency-locked loop (AFLL) that provides a clock signal, wherein the first sub-frequency-locked loop includes:
a first digitally controlled oscillator (DCO) configured to output a first signal having a first fundamental frequency;
a second DCO configured to output a second signal having a second fundamental frequency;
a voltage regulator that provides a power-supply voltage to the second DCO;
and
control logic, electrically coupled to the first DCO and the second DCO, configured to select one of the first DCO and the second DCO based on an instantaneous value of the power-supply voltage and an average power-supply voltage, wherein the AFLL is configured to modify a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage, wherein the first DCO is associated with a time-critical path having a gate-dominated delay characteristic and the second DCO is associated with a time-critical path having a wire-dominated delay characteristic.

6 more elements

Dependencies are inferred from the claim text.

AFLL with increased timing margin

Life of this patent

AFLL with increased timing margin

Life of this patent

Abstract

Claims18