Wave clocking
AssigneeBroadcom Corporation
InventorTim Sippel
Life of this patent
Estimating the term…
Abstract
Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.
Claims20
A system for generating a clock signal in an integrated circuit (IC), comprising:
- a wave clocking circuit configured to generate the clock signal;
- a frequency monitor circuit configured to directly compare a frequency of the clock signal with a target frequency to generate a frequency error;
- and
- a control circuit configured to generate a control signal based on the frequency error, the control signal being configured to adjust the frequency of the clock signal to reduce the frequency error,
- wherein the wave clocking circuit comprises a delay chain with a delay matched to a predetermined delay, and
- wherein the control signal is configured to adjust a supply voltage of the IC.
A method for generating a clock signal for an integrated circuit (IC), comprising:
- generating a signal having a period that matches substantially a predetermined delay;
- designating the signal as the clock signal;
- directly comparing a frequency of the clock signal with a target frequency to generate a frequency error;
- generating a control signal based on the frequency error, the control signal being configured to adjust the frequency of the clock signal to reduce the frequency error;
- and
- adjusting a supply voltage of the IC responsive to the control signal.
A system for generating a clock signal for an integrated circuit (IC), comprising:
- a wave clocking circuit configured to generate the clock signal;
- a frequency monitor circuit configured to directly compare a frequency of the clock signal with a target frequency to generate a frequency error;
- and
- a control circuit configured to generate a control signal based on the frequency error, the control signal being configured to adjust the frequency of the clock signal to reduce the frequency error,
- wherein the control signal is further configured to adjust a supply voltage of the IC.
Dependencies are inferred from the claim text.