Gated differential logic circuit

A method of operating a gated differential logic circuit having a first and a second driver circuit, at least one header device, at least one footer device, and at least one feedback path, the method comprising:

• receiving a differential input signal at the first and second driver circuits;
• generating, in response to receiving the differential input signal, a differential output signal from the first and second driver circuits;
• providing a feedback voltage across the at least one feedback path between a power terminal of the first driver circuit and a ground terminal of the second driver circuit,
• wherein the power terminal is coupled to a power supply by the at least one header device,
• wherein the ground terminal is coupled to ground by the at least one footer device;
• and
• injecting, in response to the feedback voltage, a current associated with the at least one feedback path into the power terminal and the ground terminal to reduce jitter in the differential output signal.

A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure specifying a gated differential logic circuit coupled to a supply voltage and to a ground, the design structure comprising:

• a first header device having a first terminal and a second terminal, the first terminal coupled to the supply voltage;
• a second header device having a third terminal and a fourth terminal, the third terminal coupled to the supply voltage;
• a first footer device having a fifth terminal and a sixth terminal, the fifth terminal coupled to the ground;
• a second footer device having a seventh terminal and an eighth terminal, the seventh terminal coupled to the ground;
• a first driver circuit having a first supply terminal coupled to the second terminal and a first ground terminal coupled to the sixth terminal;
• a second driver circuit having a second supply terminal coupled to the fourth terminal and a second ground terminal coupled to the eighth terminal;
• a first capacitor coupled between the first supply terminal and the second ground terminal;
• and
• a second capacitor coupled between the second supply terminal and the first ground terminal.