Level shifter for a time-varying input

A design structure tangibly embodied in a machine readable storage medium used in a design process, the design structure specifying a level shifter circuit for coupling a first circuit with a second circuit, the first circuit using a first supply voltage and the second circuit using a second supply voltage, the design structure comprising:

• an input node to receive an input signal;
• an output node to output to a level-shifted output signal corresponding with the input signal;
• a detection sub-circuit to detect an idle state on the input node, the detection sub-circuit having a capacitive element and a second resistive element, the idle state being a state that corresponds with a particular binary logic value and which is maintained for a first time period, wherein the first time period is determined by the capacitive element and the second resistive element;
• a first inverter that uses the second supply voltage, the first inverter having an input and an output;
• and
• a feedback path between the input and output of the first inverter, the feedback path including a first resistive element and a first transmission gate, the first transmission gate configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit.