Testable power-on-reset circuit

An integrated circuit, comprising:

• a voltage divider for receiving a first supply voltage and outputting a second supply voltage;
• a power-on-reset (POR) circuit connected to the voltage divider for receiving the second supply voltage and generating a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold;
• a first transistor having a source terminal connected to the voltage divider for receiving the second supply voltage and a gate terminal connected to the POR circuit for receiving the POR voltage signal;
• a second transistor having a source terminal connected to ground, a gate terminal connected to the POR circuit for receiving the POR voltage signal, and a drain terminal connected to a drain terminal of the first transistor for generating an inverted POR voltage signal;
• a third transistor having a source terminal connected to ground and a gate terminal connected to the POR circuit for receiving the POR voltage signal;
• a fourth transistor having a source terminal connected to ground and a gate terminal connected to the drain terminal of the second transistor for receiving the inverted POR voltage signal;
• a fifth transistor having a source terminal connected to the first supply voltage, a gate terminal connected to a drain terminal of the fourth transistor, and a drain terminal connected to a drain terminal of the third transistor;
• a sixth transistor having a source terminal connected to the first supply voltage, a gate terminal connected to the drain terminal of the third transistor, and a drain terminal connected to the drain terminal of the fourth transistor for generating a level-shifted POR voltage signal;
• a buffer connected to the drain terminal of the sixth transistor for receiving the level-shifted POR voltage signal and providing a delayed level-shifted POR voltage signal;
• and
• a flip-flop having a data input terminal connected to the first supply voltage, a clock input terminal connected to the buffer for receiving the delayed level-shifted POR voltage signal, a reset input terminal connected to the drain terminal of the sixth transistor for receiving the level-shifted POR voltage signal, and an output terminal for outputting a voltage-monitor signal.

An integrated circuit, comprising:

• a voltage divider for receiving a first supply voltage and outputting a second supply voltage;
• a power-on-reset (POR) circuit connected to the voltage divider for receiving the second supply voltage and generating a POR voltage signal when the second supply voltage exceeds a POR de-assertion threshold;
• an inverter connected to the POR circuit for receiving the POR voltage signal and generating an inverted POR voltage signal;
• a level-shifter connected to the POR circuit and the inverter for receiving the POR voltage signal and the inverted POR voltage signal, respectively, and generating a level-shifted POR voltage signal;
• a buffer connected to the level-shifter for receiving the level-shifted POR voltage signal and providing a delayed level-shifted POR voltage signal;
• a flip-flop having a data input terminal for receiving the first supply voltage, a clock input terminal connected to the buffer for receiving the delayed level-shifted POR voltage signal, a reset input terminal connected to the level-shifter for receiving the level-shifted POR voltage signal, and an output terminal for outputting a voltage-monitor signal;
• and
• a processor, connected to the output terminal of the flip-flop for receiving the voltage-monitor signal, determining a voltage level of the first supply voltage when the second supply voltage equals the POR de-assertion threshold, and determining the POR de-assertion threshold based on the voltage level of the first supply voltage.