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US 9,312,842 B2Granted
Cascoded comparator with dynamic biasing for column parallel single slope ADCs
AssigneeSK hynix Inc.
InventorsJeff Rysinski, Yibing Michelle Wang, Sang-Soo Lee
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Abstract
Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.
Claims8
Circuitry for processing signals, the circuitry comprising:
- a first PMOS transistor with a source terminal coupled to a positive voltage supply;
- a drain terminal of the first PMOS transistor coupled to a source terminal of a second PMOS transistor and to a source terminal of a third PMOS transistor;
- a first NMOS transistor with a drain terminal coupled to a drain terminal of the second PMOS transistor and to a gate terminal of the second PMOS transistor;
- a second NMOS transistor with a drain terminal coupled to a drain terminal of the third PMOS transistor and to a gate terminal of the second NMOS transistor;
- a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor coupled to ground;
- an input ramp signal applied to a gate terminal of the third PMOS transistor;
- and
- an output signal provided at the source terminal of the second PMOS transistor which is coupled at the drain terminal of the second PMOS transistor and at the drain terminal of the first NMOS transistor.
5 more elements
Dependencies are inferred from the claim text.