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US 9,312,841 B2Granted
Cascoded comparator with dynamic biasing for column parallel single slope ADCs
AssigneeSK hynix Inc.
InventorsJeff Rysinski, Yibing Michelle Wang, Sang-Soo Lee
Life of this patent
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Abstract
Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.
Claims4
Circuitry for processing signals, the circuitry comprising:
- a first PMOS transistor with a source terminal coupled to a positive voltage supply;
- a drain terminal of the first PMOS transistor coupled to a source terminal of each of a second PMOS transistor and a third PMOS transistor;
- a fourth PMOS transistor with a source terminal coupled to the drain terminal of the second PMOS transistor;
- a fifth PMOS transistor with a source terminal coupled to the drain terminal of the third PMOS transistor;
- a first NMOS transistor with a drain terminal coupled to a drain terminal of the fourth PMOS transistor, to a gate terminal of the first NMOS transistor, to a drain terminal of a second NMOS transistor, and to a gate terminal of a third NMOS transistor;
- a fourth NMOS transistor with a drain terminal coupled to a drain terminal of the fifth PMOS transistor, to a gate terminal of the fourth NMOS transistor, and to a drain terminal of the third NMOS transistor, and to a gate terminal of the second NMOS transistor;
- a source terminal of each of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor coupled to ground;
- an input ramp signal applied to a gate terminal of the second PMOS transistor and to an input terminal of a cascode bias generator;
- an input pixel signal applied to a gate terminal of the third PMOS transistor;
- the cascode bias generator having an output terminal coupled to a gate terminal of the fourth PMOS transistor and to a gate terminal of the fifth PMOS transistor;
- and
- the cascode bias generator being configured to produce a cascode biasing signal based on the input ramp signal and provide the cascode biasing signal at its output terminal.
9 more elements
Dependencies are inferred from the claim text.