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AssigneeAnalog Devices Global
InventorsYunzhi Dong, Zhao Li, Richard E. Schreier, Hajime Shibata, Trevor Clifford Caldwell
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This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.
A continuous time (CT) delay line for delaying a differential analog input pair in an analog-to-digital converter comprising a circuit producing a residual signal, the CT delay line comprising:
A continuous time (CT) delay line for delaying a differential analog input pair in a circuit producing a residual signal, the CT delay line comprising:
A plurality of continuous time (CT) delay lines implemented in an integrated circuit chip, wherein each of the CT delay lines comprises:
A circuit comprising:
Dependencies are inferred from the claim text.