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US 9,312,839 B2Granted
Buffer circuit and semiconductor integrated circuit
AssigneeSocionext Inc.
InventorRyoichi Inagawa
Life of this patent
Estimating the term…
Abstract
A buffer circuit section receives an input clock, and outputs an output clock by wave-shaping the input clock, a measurement circuit section measures a first pulse width at a first potential level of the output clock and a second pulse width at a second potential level of the output clock, and an adjustment circuit section adjusts a ratio between the first pulse width and the second pulse width by varying a drive capability of the buffer circuit section on the basis of the measurement result of the measurement circuit section.
Claims10
A buffer circuit comprising:
- a buffer circuit section which includes a plurality of transistors, receives an input clock, and outputs an output clock by wave-shaping the input clock;
- a measurement circuit section which measures a first pulse width at a first potential level of the output clock and a second pulse width at a second potential level of the output clock;
- and
- an adjustment circuit section which keeps changing a combination of first transistors to activate among the plurality of transistors regardless of a measurement result of the measurement circuit section until the adjustment circuit section activates all combinations of the plurality of transistors and the measurement circuit section completes measurement of the first pulse width and the second pulse width in all the combinations to be activated, detects a first combination by which a ratio between the first pulse width and the second pulse width becomes closest to a target ratio among all the combinations to be activated on the basis of the measurement result of the measurement circuit section after the measurement circuit section completes the measurement, and adjusts the ratio by varying a drive capability of the buffer circuit section by activating second transistors being included in the first combination and deactivating a third transistor being excluded from the first combination.
1 more element
A semiconductor integrated circuit comprising:
- a circuit section which operates in synchronization with a clock;
- and
- a buffer circuit included in a clock path which supplies the clock to the circuit section, wherein
- the buffer circuit includes:
- a buffer circuit section which includes a plurality of transistors, receives an input clock, and outputs an output clock by wave-shaping the input clock;
- a measurement circuit section which measures a first pulse width at a first potential level and a second pulse width at a second potential level of the output clock;
- and
- an adjustment circuit section which keeps changing a combination of first transistors to activate among the plurality of transistors regardless of a measurement result of the measurement circuit section until the adjustment circuit section activates all combinations of the plurality of transistors and the measurement circuit section completes measurement of the first pulse width and the second pulse width in all the combinations to be activated, detects a first combination by which a ratio between the first pulse width and the second pulse width becomes closest to a target ratio among all the combinations to be activated on the basis of the measurement result of the measurement circuit section after the measurement circuit section completes the measurement, and adjusts the ratio by varying a drive capability of the buffer circuit section by activating second transistors being included in the first combination and deactivating a third transistor being excluded from the first combination.
5 more elements
Dependencies are inferred from the claim text.