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US 9,312,838 B2Granted
Apparatus and method for transferring multiple asynchronous clock signals over a single conductor
AssigneeAlcatel Lucent
InventorsJeffrey L. Zwiebel, Andrea Galbiati
Life of this patent
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Abstract
Methods and systems for transferring two clock signals over a single conductor are disclosed. According to various disclosed embodiments, first and second input clock signals are generated at a first module. The rising and falling edges of a generated reference clock signal are used to transfer the two clock signals from the first module to a second module over the single conductor.
Claims18
An apparatus, comprising:
- first and second clocks operable to generate first and second input clock signals, respectively, wherein the first and second input clock signals are asynchronous in relation to one another;
- a first edge detector configured to receive the first input clock signal, the first edge detector operable to detect a rising edge of the first input clock signal and to generate a first enable signal;
- a second edge detector configured to receive the second input clock signal, the second edge detector operable to detect the rising edge of the second input clock signal and to generate a second enable signal;
- a first divider configured to receive the first enable signal and operable to generate a first adjusted enable signal based on a first predetermined factor;
- and
- a dual clock generator configured to receive the first adjusted enable signal and the second enable signal, and in response operable to generate a reference clock signal and transmit the reference clock signal over a single conductor.
3 more elements
An apparatus comprising:
- a first edge detector configured to receive a reference clock signal via a single conductor, the first edge detector operable to detect a rising edge of the reference clock signal and to generate a first enable signal;
- a second edge detector configured to receive the reference clock signal via the single conductor, the second edge detector operable to detect a falling edge of the reference clock signal and to generate a second enable signal;
- a first controlled oscillator configured to receive the first enable signal and operable to track the first enable signal to generate a first output clock signal;
- an integer controlled oscillator configured to receive the second enable signal and operable to generate a third enable signal that compensates the rate of the second enable signal;
- and
- a second controlled oscillator configured to receive the third enable signal and operable to track the third enable signal to generate a second output clock signal.
3 more elements
A method for transferring two asynchronous clock signals over a single conductor, comprising:
- generating, at a first module, first and second input clock signals;
- detecting, at the first module, a rising edge of the first input clock signal, and in response generating a first enable signal;
- detecting, at the first module, a rising edge of the second input clock signal, and in response generating a second enable signal;
- inserting a guard time between the first and the second enable signals to prevent overlap of the first and the second enable signals;
- generating, at the first module, a reference clock signal responsive to the first and second enable signals, wherein the reference clock signal is representative of the first and second input clock signals;
- receiving, by a second module over the single conductor, the reference clock signal;
- detecting, at the second module, rising and falling edges of the reference clock signal, and in response generating third and fourth enable signals, respectively;
- generating, at the second module, a first output clock signal by sampling the third enable signal;
- generating, at the second module, a fifth enable signal that compensates the rate of the fourth enable signal;
- generating, at the second module, a second sampled output clock signal by sampling the fifth enable signal.
7 more elements
Dependencies are inferred from the claim text.