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US 9,312,834 B1Granted
Low leakage flip-flop circuit
AssigneeFreescale Semiconductors, Inc.
InventorsMohit Parnami, Gaurav Goyal
Life of this patent
Estimating the term…
Abstract
An integrated circuit having reduced power consumption includes a clock-gating cell, a transistor and a flip-flop. The clock-gating cell receives a dynamic enable signal, generates a latched-enable signal and gates a clock signal provided to the flip-flop. The flip-flop includes first and second latches. The transistor receives an inverted latched-enable signal from the clock-gating cell and switches ON or OFF based on the logic state of the inverted latched-enable signal. The transistor provides a voltage signal to the flip-flop circuit based on the state of the flip-flop in order to control the state of the flip-flop, which reduces power consumption of the integrated circuit.
Claims20
An integrated circuit, comprising:
- a clock-gating cell for receiving an enable signal and a clock signal and generating a gated-clock signal and a latched-enable signal;
- a transistor having a gate terminal connected to the clock-gating cell by way of a first NOT gate for receiving an inverted latched-enable signal, a first diffusion terminal for receiving a supply voltage signal, and a second diffusion terminal for providing the supply voltage signal when the inverted latched-enable signal is in a first logic state;
- a first latch having an input terminal for receiving an input signal, a first power terminal connected to the second diffusion terminal of the transistor for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal connected to the clock-gating cell for receiving the gated-clock signal, and an output terminal for outputting an intermediate output signal;
- and
- a second latch having an input terminal connected to the output terminal of the first latch for receiving the intermediate output signal, a first power terminal for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal connected to the clock-gating cell by way of a second NOT gate for receiving an inverted gated-clock signal, and an output terminal for outputting an output signal.
2 more elements
An integrated circuit, comprising:
- a clock-gating cell for receiving an enable signal and a clock signal and generating a gated-clock signal and a latched-enable signal;
- a first latch having an input terminal for receiving an input signal, a first power terminal for receiving a supply voltage signal, a clock terminal connected to the clock-gating cell for receiving the gated-clock signal, and an output terminal for outputting an intermediate output signal;
- a second latch having an input terminal connected to the output terminal of the first latch for receiving the intermediate output signal, a first power terminal for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal connected to the clock-gating cell by way of a first NOT gate for receiving an inverted gated-clock signal, and an output terminal for outputting an output signal;
- and
- a transistor having a gate terminal connected to the clock-gating cell for receiving a latched-enable signal, a first diffusion terminal connected to a second power terminal of the first latch, and a second diffusion terminal connected to ground, wherein the transistor is switched on when the latched-enable signal is in a first logic state.
2 more elements
An integrated circuit, comprising:
- a first latch having an input terminal for receiving an enable signal, a first power terminal for receiving a supply voltage signal, a second power terminal connected to ground, a clock terminal for receiving a clock signal, and an output terminal for generating a latched-enable signal;
- an AND gate having a first input terminal connected to the output terminal of the first latch for receiving the latched-enable signal, a second input terminal for receiving the clock signal, and an output terminal for generating a gated-clock signal;
- a p-channel metal oxide semiconductor (PMOS) transistor having a gate terminal connected to the output terminal of the first latch by way of a first NOT gate for receiving an inverted latched-enable signal, a first diffusion terminal for receiving the supply voltage signal, and a second diffusion terminal for providing the supply voltage signal when the inverted latched-enable is in a first logic state;
- a second latch having an input terminal for receiving an input signal, a first power terminal connected to the second diffusion terminal of the PMOS transistor for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal connected to the output terminal of the AND gate for receiving the gated-clock signal, and an output terminal for outputting an intermediate output signal;
- and
- a third latch having an input terminal connected to the output terminal of the second latch for receiving the intermediate output signal, a first power terminal for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal connected to the output terminal of the AND gate by way of a second NOT gate for receiving an inverted gated-clock signal, and an output terminal for outputting an output signal.
3 more elements
Dependencies are inferred from the claim text.