Method and circuit for controlled gain reduction of a differential pair

A method for controlling the gain of a differential amplification stage of a multi-stage amplifier, the method comprising

• providing a stage output voltage at a stage output node of a differential transistor pair, based on a first input voltage at a first stage input node and a second input voltage at a second stage input node;
• wherein the differential transistor pair further comprises a reference node;
• providing an active load for the differential transistor pair, the active load comprising a first diode transistor coupled to the reference node and a first mirror transistor coupled to the stage output node;
• providing a gain control circuit arranged in parallel to the active load, the gain control circuit comprising a second diode transistor coupled to the stage output node and a second mirror transistor coupled to the reference node;
• providing a second amplification stage comprising an amplifier current source configured to provide an amplifier current;
• and an amplifier transistor arranged in series with the amplifier current source;
• wherein a gate of the amplifier transistor is coupled to the stage output node of the differential amplification stage;
• providing an output amplification stage configured to provide a load current at an amplifier output voltage to a load;
• wherein an input of the output amplification stage is coupled to an output of the second amplification stage;
• and
• providing voltage sensing means configured to provide an indication of the amplifier output voltage;
• wherein the indication of the amplifier output voltage is fed back as the first input voltage to the first stage input node.