Amplifier input stage and amplifier

An amplifier comprising:

• an amplifier input stage comprising:
• first and second p-type transistors, wherein sources of the first and second p-type transistors are connected to a first node, a drain of the first p-type transistor is connected to a first output of the amplifier input stage, a drain of the second p-type transistor is connected to a second output of the amplifier input stage, a gate of the first p-type transistor is configured to receive a first signal of an input stage differential input signal and a gate of the second p-type transistor is configured to receive a second signal of the input stage differential input signal;
• first and second n-type transistors, wherein sources of the first and second n-type transistors are connected to a second node, a drain of the first n-type transistor is connected to a third output of the amplifier input stage, a drain of the second n-type transistor is connected to a fourth output of the amplifier input stage, a gate of the first n-type transistor is configured to receive the first signal of the input stage differential input signal and a gate of the second n-type transistor is configured to receive the second signal of the input stage differential input signal;
• a first circuit arranged to provide a first portion of a first bias current to the first node;
• and
• a second circuit arranged to draw a second portion of the first bias current from the second node;
• wherein rates at which the first and second portions change are determined by a slope of a first signal of an amplifier input signal;
• and
• a further amplifier stage coupled to the first, second, third and fourth outputs of the amplifier input stage.

An amplifier input stage comprising:

• first and second p-type transistors, wherein sources of the first and second p-type transistors are coupled to a first node, a drain of the first p-type transistor is coupled to a first output of the amplifier input stage, a drain of the second p-type transistor is coupled to a second output of the amplifier input stage, a gate of the first p-type transistor is configured to receive a first signal of an input stage differential input signal and a gate of the second p-type transistor is configured to receive a second signal of the input stage differential input signal;
• first and second n-type transistors, wherein sources of the first and second n-type transistors are coupled to a second node, a drain of the first n-type transistor is coupled to a third output of the amplifier input stage, a drain of the second n-type transistor is coupled to a fourth output of the amplifier input stage, a gate of the first n-type transistor is configured to receive the first signal of the input stage differential input signal and a gate of the second n-type transistor is configured to receive the second signal of the input stage differential input signal;
• a first circuit arranged to source a first portion of a first bias current to the first node;
• and
• a second circuit arranged to source a second portion of the first bias current to the second node;
• and
• a third circuit arranged to determine the first and second portions of the bias current, the third circuit comprising:
• a current source electrically coupled to a third node;
• third and fourth transistors of a same conductivity type, the third and fourth transistors each coupled to the third node;
• wherein the first and second portions of the bias current are determined at least partly by an amplifier input signal applied to a gate of the third transistor;
• wherein the first portion of the bias current is proportional to a current flowing through the third transistor;
• and
• wherein the second portion of the bias current is proportional to a current flowing through the fourth transistor.