Switched-mode power converter with split partitioning
AssigneeInfineon Technologies Austria AG
InventorsChristoph Sandner, Roman Riederer, Josef Höglauer, Stephan Auer
Life of this patent
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Abstract
A power converter is described that includes components arranged within a first die and a second die of a single package. The first die includes one or more first switches coupled to a switching node of a power stage. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.
Claims19
A power converter comprising:
- a FET or SFET type die including one or more FET or SFET type switches coupled to a switching node of a power stage;
- and
- a CMOS type die including:
- one or more CMOS type switches coupled to the switching node of the power stage;
- one or more sense lines contained to the CMOS type die to prevent electromagnetic interference associated with the one or more FET or SFET type switches of the FET or SFET type die, the one or more sense lines being configured to transmit a sense-FET current sensing signal associated with the one or more CMOS type switches;
- and
- a controller unit configured to control the one or more FET or SFET type switches and the one or more CMOS type switches of the power stage based at least in part on the sense-FET current sensing signal that is transmitted by the one or more sense lines to produce a power output at the switching node of the power stage.
A method comprising:
- detecting, by a feedback control unit at a CMOS type die of a power converter, a current level at one or more CMOS type switches at the CMOS type die of the power converter based on a sense-FET current sensing signal associated with the one or more CMOS type switches that is being transmitted via one or more sense lines contained to the CMOS type die, wherein:
- the one or more sense lines are contained to the CMOS type die to prevent electromagnetic interference associated with one or more FET or SFET type switches at a FET or SFET type die of the power converter;
- and
- the one or more CMOS type switches are coupled to the one or more FET or SFET type switches at the FET or SFET type die of the power converter at a switching node of a power stage of the power converter;
- controlling, by a controller unit at the FET or SFET type die, the one or more FET or SFET type switches of the power stage at the FET or SFET type die based at least in part on a driver signal, wherein the driver signal is based at least in part on the current level detected at the one or more CMOS type switches at the CMOS type die;
- and
- controlling, by the controller unit at the CMOS type die, the one or more CMOS type switches of the power stage at the CMOS type die based at least in part on the driver signal.
A power converter comprising:
- means for detecting a current level at one or more CMOS type switches at a CMOS type die of a power converter based on a sense-FET current sensing signal associated with the one or more CMOS type switches that is being transmitted via one or more sense lines contained to the CMOS type die, wherein:
- the one or more sense lines are contained to the CMOS type die to prevent electromagnetic interference associated with one or more FET or SFET type switches at a FET or SFET type die of the power converter;
- and
- the one or more CMOS type switches being coupled to the one or more FET or SFET type switches at the FET or SFET type die of the power converter at a switching node of a power stage of the power converter;
- means for controlling, from the CMOS type die, the one or more FET or SFET type switches of the power stage at the FET or SFET type die based at least in part on a driver signal, wherein the driver signal is based at least in part on the current level detected at the one or more CMOS type switches at the CMOS type die;
- and
- means for controlling, from the CMOS type die, the one or more CMOS type switches of the power stage at the CMOS type die based at least in part on the driver signal.
Dependencies are inferred from the claim text.