Memory structure and preparation method thereof
AssigneeNational Chiao Tung University
InventorsPo-Tsun Liu, Yang-Shun Fan, Chun-Ching Chen
Life of this patent
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Abstract
A memory structure includes a control unit and a memory unit electrically connected to the control unit. The control unit includes a source and a drain; an active layer in contact with a portion of the source and a portion of the drain; a gate layer; and a gate insulation layer disposed between the active layer and the gate layer. The memory unit includes a bottom electrode layer; a top electrode layer; and a resistive switching layer interposed between the bottom electrode layer and the top electrode layer, which the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO).
Claims4
A method of forming a memory structure, comprising:
- forming a control unit, comprising:
- providing a gate layer;
- annealing the gate layer in wet oxygen to form a gate insulation layer on the gate layer;
- sputtering an active layer on the gate insulation layer;
- and
- depositing a source and a drain respectively on opposite sides of the active layer;
- and
- forming a memory unit on the control unit, comprising:
- depositing a bottom electrode layer on the drain;
- sputtering a resistive switching layer on the bottom electrode layer, wherein the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO);
- and
- depositing a top electrode layer on the resistive switching layer.
Dependencies are inferred from the claim text.