Single photon avalanche diode imaging sensor for complementary metal oxide semiconductor stacked chip applications

An integrated circuit system, comprising:

• a first wafer having a plurality of first dies, each first die including:
• a single photon avalanche diode (SPAD) imaging array including a plurality of pixels formed in a first semiconductor layer, wherein the plurality of pixels include an N number of pixels, wherein substantially an entire thickness of the first semiconductor layer of each pixel is fully depleted such that a multiplication region included in each pixel near a front side of the first semiconductor layer is configured to be illuminated with photons through a back side of the first semiconductor layer and through the substantially entire thickness of the fully depleted first semiconductor layer;
• deep n type isolation regions disposed in the first semiconductor layer between the pixels to isolate each one of the plurality of pixels from one another;
• a first interconnect layer disposed on the front side of the first semiconductor layer;
• and
• a second wafer having a plurality of second dies, each second die including:
• a second interconnect layer disposed on the second semiconductor layer, wherein the first wafer is bonded to the second wafer at a bonding interface between the first interconnect layer and the second interconnect layer;
• a plurality of digital counters formed in the second semiconductor layer and electrically coupled to the SPAD imaging array by way of the first and second interconnect layers, wherein the plurality of digital counters includes at least N number of digital counters, wherein each of the N number of digital counters are coupled to count output pulses generated by a respective SPAD region;
• and
• control circuitry coupled to the SPAD imaging array to control operation of the SPAD imaging array.