Methods of forming FinFET devices with alternative channel materials
AssigneeGlobalfoundries Inc.
InventorsAjey Poovannummoottil Jacob, Murat Kerem Akarvardar, Michael Hargrove, Ruilong Xie
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Abstract
Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.
Claims20
A method of forming a FinFET device in and above a substrate comprised of silicon, comprising:
- forming a doped fin for said device, said doped fin comprising a doped region that extends at least throughout a vertical height and a lateral width of said doped fin and at least into a portion of said substrate positioned vertically under said doped fin;
- forming a layer of germanium, silicon/germanium (SixGe1-x) or a III-V semiconductor material around at least a portion of said doped fin;
- and
- forming a gate structure around at least a portion of said layer of germanium, silicon/germanium or III-V semiconductor material above said portion of said doped fin to define a channel region of said FinFET device in said portion of said layer of germanium, silicon/germanium or III-V semiconductor material, wherein said gate structure includes a gate insulation layer formed above said layer of germanium, silicon/germanium or III-V semiconductor material and a gate electrode formed above said gate insulation layer.
A method of forming a FinFET device in and above a substrate comprised of silicon, comprising:
- forming a doped fin for said device, said doped fin comprising a doped region that extends at least throughout a vertical height and a lateral width of said doped fin and at least into a portion of said substrate positioned vertically under said doped fin and wherein said doped region has a dopant concentration of at least 1-3×1018 ions/cm3 of a P-type dopant or an N-type dopant;
- forming a diffusion blocking layer on and in contact with at least a portion of said doped fin,
- forming a layer of germanium, silicon/germanium or III-V semiconductor material on and in contact with said diffusion blocking layer;
- and
- forming a gate structure around at least a portion of said layer of germanium, silicon/germanium or III-V semiconductor material above said portion of said doped fin to define a channel region of said FinFET device in said portion of said layer of germanium, silicon/germanium or III-V semiconductor material, wherein said gate structure includes a gate insulation layer formed above said layer of germanium, silicon/germanium or III-V semiconductor material and a gate electrode formed above said gate insulation layer.
A FinFET device formed in and above a substrate comprised of silicon, comprising:
- a fin comprised of silicon, said fin comprising an upper surface and a plurality of sidewall surfaces;
- a doped region that extends at least throughout a vertical height and a lateral width of said fin and at least into a portion of said substrate that is positioned vertically under said fin;
- a layer of germanium, silicon/germanium or III-V semiconductor material positioned around said upper surface and said sidewall surfaces of said fin;
- and
- a gate structure positioned around said layer of germanium, silicon/germanium or III-V semiconductor material above said doped region, wherein a channel region of said FinFET device is defined in said layer of germanium, silicon/germanium or III-V semiconductor material, and said gate structure includes a gate insulation layer formed above said layer of germanium, silicon/germanium or III-V semiconductor material and a gate electrode formed above said gate insulation layer.
Dependencies are inferred from the claim text.