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US 9,312,383 B1Granted
Self-aligned contacts for vertical field effect transistors
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Wilfried Ernst-August Haensch, Ali Khakifirooz, Davood Shahrjerdi
Life of this patent
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Abstract
Semiconductor devices having vertical field effect transistors with self-aligned source and drain contacts are provided, as well as methods for fabricating vertical field effect transistors with self-aligned source and drain contacts.
Claims20
A method of forming a semiconductor device, comprising:
- patterning a semiconductor structure from an active semiconductor layer of a substrate, the patterned semiconductor structure comprising a planar semiconductor slab, and first and second semiconductor fins vertically extending from the planar semiconductor slab;
- forming a first insulating spacer to cover the planar semiconductor slab;
- forming a first gate structure around a lower portion of the first semiconductor fin and a second gate structure around a lower portion of the second semiconductor fin;
- forming a second insulating spacer which covers a least a portion of the first and second gate structures surrounding the first and second semiconductor fins, and which fills a space between the first and second gate structures;
- forming first and second source/drain structures on exposed portions of the first and second semiconductor fins extending from the second insulating spacer;
- forming a third source/drain structure on an exposed portion of the planar semiconductor slab adjacent the first and second insulating spacers;
- forming a pre-metal dielectric layer over the substrate;
- and
- forming first and second conductive via contacts in the pre-metal dielectric layer, wherein the first conductive via contact is formed self-aligned to the first and second source/drain structures, and wherein the second conductive via contact is formed self-aligned to the third source/drain structure.
6 more elements
A semiconductor integrated circuit device formed by a method comprising:
- patterning a semiconductor structure from an active semiconductor layer of a substrate, the patterned semiconductor structure comprising a planar semiconductor slab, and first and second semiconductor fins vertically extending from the planar semiconductor slab;
- forming a first insulating spacer to cover the planar semiconductor slab;
- forming a first gate structure around a lower portion of the first semiconductor fin and a second gate structure around a lower portion of the second semiconductor fin;
- forming a second insulating spacer which covers a least a portion of the first and second gate structures surrounding the first and second semiconductor fins, and which fills a space between the first and second gate structures;
- forming first and second source/drain structures on exposed portions of the first and second semiconductor fins extending from the second insulating spacer;
- forming a third source/drain structure on an exposed portion of the planar semiconductor slab adjacent the first and second insulating spacers;
- forming a pre-metal dielectric layer over the substrate;
- and
- forming first and second conductive via contacts in the pre-metal dielectric layer, wherein the first conductive via contact is formed self-aligned to the first and second source/drain structures, and wherein the second conductive via contact is formed self-aligned to the third source/drain structure.
6 more elements
A semiconductor device, comprising:
- a patterned semiconductor structure patterned from an active semiconductor layer of a substrate, the patterned semiconductor structure comprising a planar semiconductor slab, and first and second semiconductor fins vertically extending from the planar semiconductor slab;
- a first insulating spacer which covers the planar semiconductor slab;
- a first gate structure disposed around a lower portion of the first semiconductor fin;
- a second gate structure disposed around a lower portion of the second semiconductor fin;
- a second insulating spacer which covers a least a portion of the first and second gate structures surrounding the first and second semiconductor fins and which fills a space between the first and second gate structures;
- first and second source/drain structures formed on exposed portions of the first and second semiconductor fins extending from the second insulating spacer;
- a third source/drain structure formed on an exposed portion of the planar semiconductor slab adjacent the first and second insulating spacers;
- a pre-metal dielectric layer disposed over the substrate;
- and
- first and second conductive via contacts formed in the pre-metal dielectric layer, wherein the first conductive via contact is self-aligned to the first and second source/drain structures, and wherein the second conductive via contact is self-aligned to the third source/drain structure.
7 more elements
Dependencies are inferred from the claim text.