Processing of integrated circuit for metal gate replacement

A replacement metal gate (RMG) process comprising:

• providing a structure including:
• a first semiconductor fin positioned over a buried insulator layer,
• a second semiconductor fin positioned over the buried insulator layer,
• a dielectric layer positioned over the buried insulator layer, the first semiconductor fin, and the second semiconductor fin, wherein the dielectric layer includes a first trench over the first semiconductor fin and a second trench over the second semiconductor fin, and
• a gate structure positioned over the first semiconductor fin, the second semiconductor fin, and the dielectric layer, wherein the gate structure includes a gate dielectric layer and a metal layer positioned over the gate dielectric layer;
• forming a planarizing resist on the structure, the planarizing resist including:
• a first organic planarizing layer (OPL), and
• a second OPL over the first OPL, wherein an etch selectivity of the second OPL is greater than an etch selectivity of the first OPL, to enable a removal of the second OPL to substantially terminate before a subsequent removing of the first OPL;
• removing a portion of the second OPL to create an exposed portion of the first OPL located above the second semiconductor fin, wherein the removing substantially terminates before removal of the exposed portion of the first OPL, based on the etch selectivity of the second OPL being greater than the etch selectivity of the first OPL, and wherein an upper surface of the exposed portion of the first OPL is positioned above an upper surface of the second trench;
• removing at least the exposed portion of the first OPL and a portion of the metal layer positioned over the second semiconductor fin to expose the gate dielectric layer over the second semiconductor fin;
• and
• forming a metal gate stack over the gate dielectric layer over the second semiconductor fin.

A method of processing an integrated circuit (IC) structure for metal gate replacement, the method comprising:

• providing a structure including:
• a first semiconductor fin positioned over a buried insulator layer,
• a second semiconductor fin positioned over the buried insulator layer,
• a dielectric layer positioned over the buried insulator layer, the first semiconductor fin, and the second semiconductor fin, wherein the dielectric layer includes a first trench over the first semiconductor fin and a second trench over the second semiconductor fin, and
• a gate structure positioned over the first semiconductor fin, the second semiconductor fin, and the dielectric layer, wherein the gate structure includes a gate dielectric layer and a metal layer positioned over the gate dielectric layer;
• forming a planarizing resist over the structure, the planarizing resist including:
• a first organic planarizing layer (OPL), and
• a second OPL positioned on the first OPL, wherein an etch selectivity of the second OPL is greater than an etch selectivity of the first OPL, to enable a removal of the second OPL to substantially terminate before a subsequent removing of the first OPL;
• removing a portion of the second OPL to create an exposed portion of the first OPL positioned above the second semiconductor fin, wherein the removing substantially terminates before removal of the exposed portion of the first OPL, based on the etch selectivity of the second OPL being greater than the etch selectivity of the first OPL, and wherein an upper surface of the exposed portion of the first OPL is positioned above an upper surface of the second trench;
• removing at least the first OPL and a portion of the metal layer positioned over the second semiconductor fin to create an exposed portion of the gate dielectric layer positioned over the second semiconductor fin;
• removing the first and second OPLs to create an exposed portion of the metal layer positioned over the first semiconductor fin;
• and
• forming a first metal gate stack within the first trench and a second metal gate stack within the second trench.