Manufacturing method of non-planar FET
AssigneeUnited Microelectronics Corp.
InventorsShih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
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Abstract
The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.
Claims10
A method of forming a non-planar FET, comprising:
- providing a substrate;
- forming a plurality of fin structures, a plurality of shallow trench isolations (STIs) encompassing the fin structures and a plurality of sub spacers disposed only at a middle sidewall of the fin structure, wherein the STIs are completely lower than the sub spacers;
- forming a gate on the fin structure;
- and
- forming a source/drain region in the fin structure.
Dependencies are inferred from the claim text.