Manufacture of a variation resistant metal-oxide-semiconductor field effect transistor (MOSFET)

A method of manufacture for a metal-oxide semiconductor field effect transistor (MOSFET), the method comprising:

• forming a poly gate over a well and using the poly gate as a mask for forming a shallow source region and a shallow drain region;
• forming spacers on the sides of the poly gate;
• sacrificing the poly gate to form a cavity between spacers;
• etching away any protective oxide within the cavity;
• etching selectively a recess into the well within the cavity, the recess having a bottom surface that is deeper than the depth of the shallow source region and the shallow drain region;
• forming in the recess a buried epitaxial layer having a first doping level and a first layer thickness;
• forming in the recess an undoped channel epitaxial layer over the buried epitaxial layer and having a second doping level and a second layer thickness, the undoped channel epitaxial layer having a thickness that reduces statistical variations of threshold voltage (σVT) of the MOSFET, the undoped channel epitaxial layer touching the shallow source region and the shallow drain region;
• forming a high-K dielectric stack over the undoped channel epitaxial layer;
• and
• forming a metal gate layer over the high-K dielectric layer;
• the forming of the undoped channel epitaxial layer, the forming the high-K dielectric stack and the forming the metal gate layer all using processes that do not exceed 900° C.

A method for manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

• etching selectively a recess into a well of a MOSFET between a shallow drain region and a shallow source region within a cavity formed between spacers of a sacrificial gate, the recess having a bottom surface that is deeper than the depth of the shallow source region and the shallow drain region;
• and
• forming an undoped channel epitaxial layer in the recess, the undoped channel epitaxial layer having a thickness that reduces statistical variations of threshold voltage (σVT) of the MOSFET;
• forming a high-K dielectric stack over the undoped channel epitaxial layer;
• and
• forming a metal gate layer over the high-K dielectric layer;
• the forming of the undoped channel epitaxial layer, the forming the high-K dielectric stack and the forming the metal gate layer all using processes that do not exceed 900° C.