Semiconductor device with a charge carrier compensation structure and method for the production of a semiconductor device
AssigneeInfineon Technologies Austria AG
InventorsAnton Mauder, Franz Hirler, Armin Willmeroth, Michael Rueb, Holger Kapels
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Abstract
A semiconductor device has a cell field with drift zones of a first type of conductivity and charge carrier compensation zones of a second type of conductivity complementary to the first type. An edge region which surrounds the cell field has a higher blocking strength than the cell field, the edge region having a near-surface area which is undoped to more weakly doped than the drift zones, and beneath the near-surface area at least one buried, vertically extending complementarily doped zone is positioned.
Claims18
A semiconductor device with a charge carrier compensation structure in a semiconductor body comprising:
- a substrate;
- a cell field comprising drift zones and charge carrier compensation zones, wherein the drift zones comprise a first type of conductivity and the charge carrier compensation zones comprise a second type of conductivity complementary to the first type of conductivity, and
- an edge region which surrounds the cell field;
- wherein the edge region comprises:
- a near-surface area which is undoped to more weakly doped than the drift zones,
- at least one buried, vertically extending, zone positioned beneath the near-surface area, the buried, vertically extending zone comprising the second type of conductivity,
- a layer forming a lateral buried field stop zone positioned above an upper side of the substrate, wherein the lateral buried field stop zone has a dopant concentration of the first conductivity type which is lower than the dopant concentration of layers of the drift zones.
A method for the production of a semiconductor device by using a multi-epitaxy process, the method comprising:
- forming a first epitaxy layer using first ion implantation masks which have first structures;
- forming at least one further epitaxy layer using second ion implantation masks which have first structures;
- wherein an edge region with buried charge carrier compensation zones is produced in the first epitaxy layer and an edge region with an undoped or weakly doped region is produced in at least one epitaxy layer;
- further comprising:
- a) providing a semiconductor wafer as a semiconductor substrate having a substrate rear-sided surface and a substrate front-sided surface and a dopant concentration;
- b) applying the first epitaxy layer, wherein the first epitaxy layer is of a first type of conductivity with a weaker dopant concentration than the dopant concentration of the semiconductor substrate;
- c) inserting dopant depots of a second type of conductivity complementary to the first type for charge carrier compensation zones in a cell field and dopant depots of an edge region surrounding the cell field with a predetermined grid pitch by masked insertion within individual semiconductor chip positions of the semiconductor wafer;
- d) repeating the steps b) and c) in near-substrate regions;
- e) applying a second epitaxy layer, wherein the second epitaxy layer is a non-doped or weakly doped epitaxy layer which is more weakly doped than the first epitaxy layers in near-substrate regions;
- f) inserting dopant depots for charge carrier compensation zones of the complementary second type of conductivity in the cell field by masked insertion;
- g) inserting dopant depots for drift zones of the first type of conductivity in the cell field with at least partial masking of the edge region in order to maintain an edge region with an un- or weakly-doped epitaxy layer close to an upper-sides surface of the semiconductor body by masked insertion;
- h) repeating the steps e) to g) in near surface regions of the semiconductor body;
- i) diffusing the dopant depots and forming vertical, interlocking regions of the same type of conductivity.
Dependencies are inferred from the claim text.