Transistors with semiconductor interconnection layers and semiconductor channel layers of different semiconductor materials

A transistor comprising:

• a semiconductor drift layer of a first semiconductor material;
• a semiconductor channel layer on the semiconductor drift layer wherein the semiconductor channel layer comprises a second semiconductor material;
• an interconnection layer electrically coupled between the semiconductor drift layer and the semiconductor channel layer, wherein the interconnection layer comprises a third material;
• and
• a control electrode on the semiconductor channel layer;
• wherein the first semiconductor material comprises silicon carbide, wherein the second semiconductor material comprises a group III nitride, and wherein the third material comprises silicon.

A transistor comprising:

• a semiconductor drift layer of a first semiconductor material;
• a semiconductor channel layer on the semiconductor drift layer wherein the semiconductor channel layer comprises a second semiconductor material;
• an interconnection layer electrically coupled between the semiconductor drift layer and the semiconductor channel layer, wherein the interconnection layer comprises a third material;
• and
• a control electrode on the semiconductor channel layer;
• wherein the interconnection layer comprises a semiconductor interconnection layer, wherein the semiconductor channel layer includes a highly doped contact region electrically coupled to the semiconductor interconnection layer, wherein the highly doped contact region, the semiconductor interconnection layer, and the semiconductor drift layer have a same conductivity type, wherein the highly doped contact region is electrically coupled between the semiconductor interconnection layer and portions of the semiconductor channel layer, and wherein portions of the highly doped contact region are physically located between portions of the semiconductor interconnection layer and portions of the semiconductor channel layer.

A transistor comprising:

• a semiconductor drift layer of a first semiconductor material;
• a semiconductor channel layer on the semiconductor drift layer wherein the semiconductor channel layer comprises a second semiconductor material;
• an interconnection layer electrically coupled between the semiconductor drift layer and the semiconductor channel layer, wherein the interconnection layer comprises a third material;
• a control electrode on the semiconductor channel layer;
• and
• a semiconductor contact region of the first semiconductor material between the semiconductor drift and interconnection layers, wherein the semiconductor drift layer and the semiconductor contact region have a same conductivity type, wherein a dopant concentration of the semiconductor contact region is greater than a dopant concentration of the semiconductor drift layer, and wherein the first and third materials are different;
• wherein an interface between the interconnection layer and the semiconductor drift layer is a direct interface between the first and third materials, and wherein a width of the interface between the interconnection layer and the semiconductor drift layer in a direction parallel to the interface is less than a greatest width of the drift layer in the direction parallel to the interface.

A transistor comprising:

• a semiconductor drift layer of a first semiconductor material and having a first conductivity type;
• a semiconductor blocking region on the semiconductor drift layer wherein the semiconductor blocking region has a second conductivity type different than the first conductivity type;
• a semiconductor channel layer on the semiconductor blocking region wherein the semiconductor channel layer comprises a second semiconductor material, and wherein the semiconductor blocking region is between the semiconductor drift and channel layers;
• an interconnection layer electrically connected between the semiconductor drift layer and the semiconductor channel layer, and wherein the interconnection layer comprises a third material;
• a first controlled electrode electrically coupled to a portion of the semiconductor channel layer spaced apart from the semiconductor interconnection layer;
• a second controlled electrode electrically coupled to the semiconductor drift layer;
• and
• a control electrode on the semiconductor channel layer between the first controlled electrode and the interconnection layer wherein the control electrode is configured to modulate an electrical conductivity of the channel layer responsive to an electrical signal applied to the control electrode;
• wherein the third material comprises polycrystalline silicon.

A transistor comprising:

• a silicon carbide drift layer wherein the silicon carbide drift layer has a first conductivity type;
• a group III nitride channel layer on the silicon carbide drift layer;
• a first controlled electrode electrically coupled to a portion of the group III nitride channel layer;
• a second controlled electrode electrically coupled to the silicon carbide drift layer;
• a control electrode on the group III nitride channel layer;
• a semiconductor blocking region between the silicon carbide drift layer and the group III nitride channel layer wherein the semiconductor blocking region has a second conductivity type different than the first conductivity type;
• and
• an interconnection layer electrically connected between the silicon carbide drift layer and the group III nitride channel layer, wherein the interconnection layer comprises a material different than the group III nitride of the group III nitride channel layer and different than silicon carbide;
• wherein the semiconductor blocking region comprises a silicon carbide blocking region, and wherein the interconnection layer comprises a polycrystalline semiconductor material.

A high electron mobility transistor (HEMT) comprising:

• a semiconductor drift layer, wherein the semiconductor drift layer comprises a silicon carbide drift layer;
• a semiconductor channel layer on the semiconductor drift layer, wherein the semiconductor channel layer includes a stack of semiconductor layers defining a heterojunction to provide a two dimensional electron gas, wherein the semiconductor channel layer comprises a group HI nitride channel layer;
• a first controlled electrode electrically coupled to a portion of the semiconductor channel layer;
• a second controlled electrode electrically coupled to the semiconductor drift layer;
• a control electrode on the semiconductor channel layer, wherein the control electrode is configured to modulate a conductivity of the two dimensional electron gas responsive to an electrical signal applied to the control electrode;
• and
• a silicon interconnection layer electrically connected between the group III nitride channel layer and the silicon carbide drift layer.