US 9,312,331 B2 · Semiconductor device

Abstract

A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided in the first semiconductor region, an element region, and a termination region. The element region includes a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, and a gate electrode disposed on a gate insulating layer that extends adjacent the third semiconductor region and the fourth semiconductor region. The termination region surrounds the element region and includes a first electrode, which includes first portions extending in a first direction and second portions extending in a second direction. A plurality of first electrodes are provided on the first semiconductor region and the second semiconductor region. An interval between adjacent first portions in the second direction is less than an interval between adjacent second portions in the first direction.

Drawings

Claims20

Dependent claims

A semiconductor device comprising:

a first semiconductor region of a first conductivity type;
a plurality of second semiconductor regions of a second conductivity type extending inwardly of the first semiconductor region, each of the plurality of second semiconductor regions extending in a first direction, and arranged along a second direction crossing the first direction;
an element region that includes a third semiconductor region of the second conductivity type that is provided on the second semiconductor regions, a fourth semiconductor region of the first conductivity type that is selectively provided on the third semiconductor region, and a gate electrode disposed on a gate insulating layer that extends adjacent the third semiconductor region and the fourth semiconductor region;
and
a termination region surrounding the element region and having a plurality of first electrodes that include respective first portions extending in the first direction and second portions extending in the second direction on the first semiconductor region and the second semiconductor region, wherein an interval between adjacent first portions in the second direction is less than an interval between adjacent second portions in the first direction.

2 more elements

A semiconductor device comprising:

a first semiconductor region of a first conductivity type;
a plurality of second semiconductor regions of a second conductivity type that are provided in the first semiconductor region in a second direction crossing a first direction, and extending in the first direction, and arranged along the second direction crossing the first direction;
an element region that includes a third semiconductor region of the second conductivity type that is provided on the second semiconductor regions, a fourth semiconductor region of the first conductivity type that is selectively provided on the third semiconductor region, and a gate electrode disposed on a gate insulating layer that extends adjacent the third semiconductor region and the fourth semiconductor region;
and
a termination region having a plurality of first electrodes that include first portions extending in the first direction and second portions extending in the second direction on the first semiconductor region and the second semiconductor region, and an insulating layer that surrounds the element region and is provided between the first semiconductor region and the plurality of first electrodes, and between the second semiconductor region and the plurality of first electrodes, wherein a film thickness of a portion of the insulating layer overlying the second portion is thicker than a film thickness of the insulating layer overlying the first portion.

2 more elements

Dependencies are inferred from the claim text.

Description7,296 words

Summary314 words

#This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-187330, filed Sep. 16, 2014, the entire contents of which are incorporated herein by reference.

#Embodiments described herein relate generally to a semiconductor device.

#A semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET,) or an insulated gate bipolar transistor (IGBT), has a super junction structure in which a p-type semiconductor region and an n-type semiconductor region are alternately provided in a drift layer in order to compensate for a design tradeoff between a breakdown voltage and on-resistance (or an on-voltage). By using the structure, it is possible to increase an effective doping concentration of the drift layer and to improve the relationship between the breakdown voltage and the on-resistance (or an on-voltage).

Brief description of the drawings11 figures

#FIG. 1 is a plan view which illustrates a semiconductor device according to a first embodiment.

#FIG. 2 is a plan view which illustrates a portion of the semiconductor device according to the first embodiment.

#FIGS. 3A and 3B are cross-sectional views which illustrate a portion of the semiconductor device according to the first embodiment. FIG. 3A is a cross-sectional view of FIG. 2 along section A-A′, and FIG. 3B is a cross-sectional view of FIG. 2 along section B-B′.

Detailed description6,670 words

#Embodiments provide a semiconductor device which may suppress a decrease in breakdown voltage.

#In general, according to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type extending inwardly of the first semiconductor region, each of the plurality of second semiconductor regions extending in a first direction, and arranged along a second direction crossing the first direction, an element region, and a termination region.

#The second semiconductor region is provided in the first semiconductor region. The second semiconductor region extends in a first direction. A plurality of the second semiconductor regions are arranged along a second direction crossing the first direction.

Facts

Application

14/637,170Filed 3 Mar 2015

Priority

JP 2014-18733016 Sep 2014

Published

US 2016/0079351 A117 Mar 2016

Granted

12 Apr 2016

Term ends

3 Mar 2035

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification11 codes

H10D 62/111
Reduced surface field [RESURF] PN junction structures: multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
H10D 12/038
Of vertical IGBTs: having a recessed gate, e.g. trench-gate IGBTs
H10D 12/481
Having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions: having gate…
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes

Timeline

16 Sep 2014Priority claimedJP 2014-187330
3 Mar 2015Application filedUS 14/637,170
3 Mar 2015Assigned to Kabushiki Kaisha Toshibaassignment of assignor's interest
17 Mar 2016PublishedUS 2016/0079351 A1
12 Apr 2016GrantedUS 9,312,331 B2
12 Oct 2026TodayWithin its term
3 Mar 2035Term endsEstimated

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims20

Description7,296 words

Drawings

Classification11 codes

Life of this patent

Description7,296 words