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US 9,312,330 B2Granted
Super-junction semiconductor device
AssigneeFuji Electric Co., Ltd.
InventorManabu Takei
Life of this patent
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Abstract
Provision of a super-junction semiconductor device capable of reducing rises in transient on-resistance at the time of repeated switching operation. A super-junction structure is provided that has a striped parallel surface pattern, where a super-junction stripe and a MOS cell 6 stripe are parallel, and a p column Y2 over which no MOS cell 6 stripe is arranged and a p column Y1 over which the MOS cell 6 stripe is arranged are connected at an end.
Claims7
A super-junction semiconductor device comprising:
- a first-conduction type of a semiconductor substrate,
- a primary plane of the first-conduction-type semiconductor substrate,
- a super-junction structure having a first primary plane and a second primary plane, wherein the primary plane of the first-conduction-type semiconductor substrate and the first primary plane are in contact with each other, and
- MOS cell structures formed on the second primary plane side of the super-junction structure,
- wherein the super-junction structure includes first-conduction-type layers and second-conduction-type layers arranged in parallel to the primary plane, alternating in position to form a stripe pattern in plain view,
- wherein the MOS cell structures include:
- high-density, second-conduction-type base regions formed to overlap along a longitudinal direction of the stripe pattern on alternating layers of the second-conduction-type layers of the second primary plane side of the super-junction structure,
- high-density, first-conduction-type source regions formed along a longitudinal direction on surface layers of the high-density, second-conduction-type base regions,
- gate electrodes formed along a longitudinal direction of the stripe pattern, through an insulation film on surfaces between the high-density, first-conduction-type source regions formed on the second-conduction-type base regions next to each other,
- wherein the second-conduction-type layers on which any of the MOS cell structures is not formed are arranged between the high-density, second-conduction-type regions next to each other in a wide direction orthogonal to the longitudinal direction of the stripe pattern,
- wherein the high-density, second-conduction-type base regions and the second-conduction-type layer on which any of the MOS cell structures is not formed are in conductive connection with each other, and wherein
- the conductive connection is by a high-density, second-conduction-type layer formed along the wide direction orthogonal to the longitudinal direction of the stripe pattern, connecting the end portion of the high-density, second-conduction-type base regions and the second-conduction-type layers.
9 more elements
A super-junction semiconductor device comprising:
- a first-conduction type of a semiconductor substrate,
- a primary plane of the first-conduction-type semiconductor substrate,
- a super-junction structure having a first primary plane and a second primary plane, wherein the primary plane of the first-conduction-type semiconductor substrate and the first primary plane are in contact with each other, and
- MOS cell structures formed on the second primary plane side of the super-junction structure,
- wherein the super-junction structure includes first-conduction-type layers and second-conduction-type layers arranged in parallel to the primary plane, alternating in position to form a stripe pattern in plain view,
- wherein the MOS cell structures include:
- high-density, second-conduction-type base regions formed to overlap along a longitudinal direction of the stripe pattern on alternating layers of the second-conduction-type layers of the second primary plane side of the super-junction structure,
- high-density, first-conduction-type source regions formed along a longitudinal direction on surface layers of the high-density, second-conduction-type base regions,
- gate electrodes formed along a longitudinal direction of the stripe pattern, through an insulation film on surfaces between the high-density, first-conduction-type source regions formed on the second-conduction-type base regions next to each other,
- wherein the second-conduction-type layers on which any of the MOS cell structures is not formed are arranged between the high-density, second-conduction-type regions next to each other in a wide direction orthogonal to the longitudinal direction of the stripe pattern,
- wherein the high-density, second-conduction-type base regions and the second-conduction-type layer on which any of the MOS cell structures is not formed are in conductive connection with each other, and wherein the conductive connection is by a conductive layer or a metal film formed so as to connect the end surface of the second-conduction-type layers of the super-junction structure.
8 more elements
Dependencies are inferred from the claim text.