Vertical cross point arrays for ultra high density memory applications

A memory structure, comprising:

• a front-end of the line (FEOL) portion comprising logic circuitry to perform data operations on memory cells of a vertical cross-point array (VCPA);
• a VCPA formed back-end of the line (BEOL) disposed over said FEOL portion, said VCPA comprising horizontal lines, vertical lines, and two-terminal memory cells integrally formed between a center conductor of each vertical line and a respective crossing horizontal line, wherein the horizontal lines comprise conductive lines bounded on both sides by an inner diffusion barrier layer and an outer edge electrode;
• a plurality of bit lines;
• a plurality of select devices disposed above, and not within said FEOL portion, said plurality of select devices operable to selectively electrically couple the center conductors of the vertical lines of said VCPA to bit lines of said plurality of bit lines;
• and
• at least one of a via or an interconnect to electrically connect bit lines of said plurality of bit lines to the logic circuitry in said FEOL portion.