Nonvolatile memory device and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorsYoshinori Nakakubo, Shigeki Kobayashi, Takeshi Yamaguchi
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Abstract
According to an embodiment, a first impurity diffusion layer is provided in a region lower than a drain region and the first impurity diffusion layer diffuses impurities of a second conductivity type. A second impurity diffusion layer is provided between the drain region and the first impurity diffusion layer, and the second impurity diffusion layer diffuses impurities of a first conductivity type or the second conductivity type, and a concentration of the second impurity diffusion layer is lower than that of the first conductivity type of the drain region and that of the second conductivity type of the first impurity diffusion layer.
Claims16
A nonvolatile memory device comprising:
- a selection transistor including a gate electrode provided above a semiconductor substrate via a gate insulating film, and source/drain regions provided on both sides of a surface of the semiconductor substrate, sandwiching the gate electrode, and the source/drain regions diffused impurities of a first conductivity type;
- a memory cell including a variable resistive layer connected to a drain region of the selection transistor and a first electrode that is formed on the variable resistive layer;
- a first impurity diffusion layer provided in a region lower than the drain region, and the first impurity diffusion layer having impurities of a second conductivity type;
- and
- a second impurity diffusion layer provided between the drain region and the first impurity diffusion layer, and the second impurity diffusion layer having impurities of the first conductivity type or the second conductivity type, and a concentration of the second impurity diffusion layer being lower than that of the first conductivity type in the drain region and that of the second conductivity type in the first impurity diffusion layer.
Dependencies are inferred from the claim text.