Method for producing display panel, and display panel

A display panel comprising:

• a base substrate;
• a gate electrode located on an upper surface of the base substrate;
• a gate insulating film located on the base substrate and having a first opening therein at a position overlapping with the gate electrode in plan-view;
• a bank layer located on the gate insulating film and having a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view;
• and
• a wiring layer located in the first opening and the second opening, in contact with the gate electrode, wherein
• the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and
• the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening.

A method for producing a transistor array, comprising:

• preparing a base substrate having an upper surface on which a gate electrode is located;
• forming a gate insulating film on the base substrate such that the gate insulating film has a first opening therein at a position overlapping with the gate electrode in plan-view;
• forming a bank layer on the gate insulating film such that the bank layer has a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view;
• and
• forming a wiring layer in the first opening and the second opening such that the wiring layer is in contact with the gate electrode, wherein
• the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and
• the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening.

A method for producing a display panel, comprising:

• preparing a base substrate having an upper surface on which a gate electrode is located;
• forming a gate insulating film on the base substrate such that the gate insulating film has a first opening therein at a position overlapping with the gate electrode in plan-view;
• forming a bank layer on the gate insulating film such that the bank layer has a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view;
• and
• forming a wiring layer in the first opening and the second opening such that the wiring layer is in contact with the gate electrode, wherein
• the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and
• the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening.