Implementing buried FET utilizing drain of finFET as gate of buried FET
AssigneeGlobalfoundries Inc.
InventorsKarl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
Life of this patent
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Abstract
A method and circuit for implementing an enhanced transistor topology with a buried field effect transistor (FET) utilizing the drain of a FinFET as the gate of the new buried FET and a design structure on which the subject circuit resides are provided. A drain area of the fin area of a FinFET over a buried dielectric layer provides both the drain of the FinFET as well as the gate node of a second field effect transistor. This second field effect transistor is buried in the carrier semiconductor substrate under the buried dielectric layer.
Claims20
A circuit for implementing an enhanced transistor topology enabling increased circuit density comprising:
- a fin field effect transistor (FinFET);
- said FinFET formed over a dielectric layer;
- a source of said FinFET having a larger width than a drain;
- a portion of said drain centered over a body region between a source and a drain of a buried field effect transistor (FET);
- said buried field effect transistor (FET) formed in a semiconductor substrate under said dielectric layer and said buried FET utilizing said drain of said FinFET as a gate node.
A method for implementing an enhanced transistor topology enabling increased circuit density comprising:
- forming a fin field effect transistor (FinFET) over a dielectric layer;
- a source of said FinFET having a larger width than a drain;
- a portion of said drain centered over a body region between a source and a drain of a buried field effect transistor (FET);
- forming said buried field effect transistor (FET) in a carrier semiconductor substrate under the dielectric layer with said buried FET utilizing said drain of said FinFET as a gate node.
A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:
- a circuit tangibly embodied in the non-transitory machine readable medium used in the design process, said circuit for implementing an enhanced transistor topology enabling increased circuit density comprising:
- a fin field effect transistor (FinFET);
- said FinFET formed over a dielectric layer;
- a source of said FinFET having a larger width than a drain;
- a portion of said drain centered over a body region between a source and a drain of a buried field effect transistor (FET);
- said buried field effect transistor (FET) formed in a semiconductor substrate under said dielectric layer and said buried FET utilizing said drain of said FinFET as a gate node, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.
Dependencies are inferred from the claim text.